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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sept. 2005

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  • Table of contents

    Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

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  • Guest Editorial

    Page(s): 1313 - 1314
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  • Delay-fault diagnosis using timing information

    Page(s): 1315 - 1325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. Unfortunately, the resolution of the existing delay-fault diagnostic methodologies is still unsatisfactory. In this paper, the feasibility of using the circuit timing information to guide the delay-fault diagnosis is investigated. A novel and efficient diagnostic approach based on the delay window propagation (DWP) is proposed to achieve significantly better diagnostic results than those of an existing delay-fault diagnostic commercial tool. Besides locating the source of the timing errors, for each identified candidate the proposed method determines the most probable delay defect size. The experimental results indicate that the new method diagnoses timing faults with very good resolution. View full abstract»

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  • Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects

    Page(s): 1326 - 1335
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    Physically based simulations are used to predict an electromigration (EM)-induced void nucleation and growth in dual-inlaid copper interconnects. Incorporation of all important atom migration driving forces into the mass balance equation and its solution together with the solution of the coupled electromagnetics, heat transfer, and elasticity problems allows one to simulate EM-induced degradation in a variety of interconnect segments characterized by different dominant channels for mass transport. The existence of the weak interfaces between copper and diffusion barriers results in different EM-induced degradation pictures in aluminum and copper interconnects. The interface bonding strengths, significantly influencing the interface diffusivity and, consequently, the mass transport along interfaces in the case of copper interconnect, result in completely different degradation and failure pictures for the weak and strengthened copper/capping layer interfaces. Strengthening of the top interface of inlaid copper interconnect metal line is a promising way to prolong the EM lifetime. The correspondence between simulation results and experimental data indicates the applicability of the developed model for the optimization of the physical and electrical design rules. By varying the interconnect architecture, segment geometry, material properties, and some of the process parameters, users will be in a position to generate on-chip interconnect systems with high immunity to EM-induced failures. View full abstract»

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  • A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects

    Page(s): 1336 - 1346
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    Performance optimization is a critical step in the design of integrated circuits. Rapid advances in very large scale integration (VLSI) technology have enabled shrinking feature sizes, wire widths, and wire spacings, making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires becomes more pronounced. Changing the relative signal arrival times (RSATs) alters the victim line delay due to the varying coupling noise on the victim line. The authors propose a sensitivity-based method to analyze delay uncertainties of coupled interconnects due to uncertain signal arrival times at its inputs. Compared to existing methods of analyzing delay uncertainties of coupled interconnects, the simulation results show that the proposed method strikes a good balance between model accuracy and complexity compared to the existing approaches. View full abstract»

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  • Calligrapher: a new layout-migration engine for hard intellectual property libraries

    Page(s): 1347 - 1361
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    Modern systems-on-a-chip depend heavily on hard intellectual properties, such as standard cell and datapath libraries. As the foundries accelerate their update of advanced processes with increasingly complex design rules, and the libraries grow in flexibility and size, the cost of library development becomes prohibitively high. Automated layout-migration techniques used today, which are based on layout compaction developed a decade ago, corrupt advanced design considerations by honoring only design rules, and cannot cope with some of the new challenges involved. In this paper, we present a new integer linear programming (ILP)-based layout-migration engine, called calligrapher, and make the following contributions. First, we extend the recently proposed minimum perturbation (MP) metric designed to retain original layout design intentions, while overcoming its shortcoming of biased treatment of layout objects. Second, we propose a new design-rule-constraint algorithm, and prove its linear complexity for the number of constraints generated. Compared with what has been achieved in the literature, the proposed algorithm can significantly reduce the ILP solver time by limiting the constraint size. Third, we propose an iterative migration framework based on the concept of soft constraint. With this framework, two-dimensional compaction quality can be achieved with a runtime comparable to one-dimensional compaction. We demonstrate the effectiveness of calligrapher by migrating the Berkeley low-power libraries, originally developed for the 1.2-μm MOSIS process, into TSMC 0.25- and 0.18-μm technologies. We show that even for a very compact layout, our metric and the MP metric can make a difference by as much as 20%-45%. We also show that our iterative algorithm can improve the area by 10% on average compared to the traditional technique using the MP metric, and inflates the area by merely 7.5% compared to the traditional technique using minimum-area metric. View full abstract»

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  • Supply and power optimization in leakage-dominant technologies

    Page(s): 1362 - 1371
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum VDD value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum VDD that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum VDD for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing VDD results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in VDD. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation. View full abstract»

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  • Application-specific worst case corners using response surfaces and statistical models

    Page(s): 1372 - 1380
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    Integrated circuits (ICs) must be robust to manufacturing variations. Circuit simulation at a set of worst case corners is a computationally efficient method for verifying the robustness of a design. This paper presents a new statistical methodology to determine the worst case corners for a set of circuit performances. The proposed methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surfaces are then used to extract the worst case corners in the process parameter space as the points where the circuit performances are at their minimum/maximum values corresponding to a specified tolerance level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. The novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level is also introduced. The corners are realistic since they are derived from the multivariate statistical distribution of the process parameters at the desired tolerance level. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/radio frequency (RF) blocks found in typical communication ICs. View full abstract»

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  • An industrially effective environment for formal hardware verification

    Page(s): 1381 - 1405
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described. View full abstract»

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  • Eliminating false positives in crosstalk noise analysis

    Page(s): 1406 - 1419
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    Noise affects circuit operation by varying circuit delays and causing latches to capture incorrect values. Conventional noise analysis techniques can detect some of such noise faults, but accurate analysis requires a careful examination of timing and functional properties of the circuit. In this paper, a method of characterizing correlation of signal transitions in nets by considering in a unified way both timing and functionality of the signals is proposed. An analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered is described. The timed-Boolean logic is used to characterize signal transitions in a time interval, and correlations are checked by solving Boolean satisfiability (SAT) between aggressor and victim transitions under the min-max delay model for gates. The method is applicable for checking noise faults at a single net, on a path, or in a cone of logic. The proposed technique is scalable as it keeps the size of Boolean formulation linear to the size of the modeled circuit. It has been applied on a set of large circuits, eliminating up to 50% of noise delay faults reported by a conventional noise-analysis method. View full abstract»

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  • Sparse transformations and preconditioners for 3-D capacitance extraction

    Page(s): 1420 - 1426
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    Three-dimensional (3-D) capacitance-extraction algorithms are important due to their high accuracy. However, the current 3-D algorithms are slow and thus their application is limited. In this paper, we present a novel method to significantly speed up capacitance-extraction algorithms based on boundary element methods (BEMs), under uniform and multiple dielectrics. The n×n coefficient matrix in the BEM is dense, even when approximated with the fast multipole method or hierarchical-refinement method, where n is the number of panels needed to discretize the conductor surfaces and dielectric interfaces. As a result, effective preconditioners are hard to obtain and iterative solvers converge slowly. In this paper, we introduce a linear transformation to convert the n×n dense coefficient matrix into a sparse matrix with O(n) nonzero entries, and then use incomplete factorization to produce a very effective preconditioner. For the k×k bus-crossing benchmark, our method requires at most four iterations, whereas previous best methods such as FastCap and HiCap require 10-20 iterations. As a result, our algorithm is up to 70 times faster than FastCap and up to 2 times faster than HiCap on these benchmarks. Additional experiments illustrate that our method consistently outperforms previous best methods by a large magnitude on complex industrial problems with multiple dielectrics. View full abstract»

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  • A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations

    Page(s): 1427 - 1443
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    In this paper, a new multilevel Green's function interpolation method (MLGFIM) is presented to solve integral equations for large-scale electrostatic problems. In MLGFIM, the problem domain is first divided into multilevel cubes. Next, the peer-level Green's function interpolation technique is employed, and then, a new lower-to-upper-level Green's function interpolation technique is devised. They are used with the multilevel discretization to speed up the matrix-vector multiplications in the iterative solution in which a computational complexity of O(N) is achieved. The MLGFIM is used to extract the capacitances encountered in radio frequency integrated circuits (RFICs) and microelectromechanical systems. Moreover, to demonstrate its efficiency both in simulation speed and memory storage requirement, MLGFIM is compared with FastCap for free space problems and applied to extract capacitances from multilayered structures. For problems with 375,000 unknowns, the proposed method only requires 343 MB of computer memory. View full abstract»

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  • Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus

    Page(s): 1444 - 1456
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    Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms. View full abstract»

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  • EBIST: a novel test generator with built-in fault detection capability

    Page(s): 1457 - 1466
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    A novel design methodology for test pattern generation in built-in self-test (BIST) is proposed. Experimental results are presented to demonstrate how a fault in the test pattern generator (TPG) itself can have serious consequences, a problem that has not been investigated. A solution is presented here, where the faults and errors in the generator itself are detected during the test in the TPG itself. This provides several major advantages, including the ability to distinguish between TPG and circuit under test (CUT) faults. In addition, this will ensure that there is no loss of fault coverage for the CUT caused by a fault in the TPG. Two different design methodologies are presented: The first guarantees all single fault/error detection, the second capable of detecting multiple faults and errors. The proposed linear feedback shift registers (LFSRs) do not have additional hardware overhead. Importantly, the test patterns generated have the potential to achieve superior fault coverage for both stuck-at and transition faults. View full abstract»

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  • Statistical timing analysis under spatial correlations

    Page(s): 1467 - 1482
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    Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance. An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented. The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal. The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo (MC) simulation. On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 1.06% and -4.34%, respectively, and the errors of predicting the 99% and 1% confidence point are -2.46% and -0.99%, respectively. A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h. View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Page(s): 1483
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  • 2006 IEEE International Conference on Multimedia and Expo (ICME)

    Page(s): 1484
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  • IEEE Circuits and Systems Society Information

    Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu