IEEE Transactions on Computers

Issue 10 • Oct. 2005

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • Guest Editors' Introduction

    Publication Year: 2005, Page(s):1185 - 1187
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  • Supporting demanding hard-real-time systems with STI

    Publication Year: 2005, Page(s):1188 - 1202
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1464 KB) | HTML iconHTML

    Software thread integration (STI) is a compilation technique which enables the efficient use of an application's fine-grain idle time on generic processors without special hardware support. With STI, a primary function is automatically interleaved with a secondary function to create a single implicitly multithreaded function which minimizes context switching and, hence, both improves performance a... View full abstract»

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  • Frequent loop detection using efficient nonintrusive on-chip hardware

    Publication Year: 2005, Page(s):1203 - 1215
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1808 KB) | HTML iconHTML

    Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting frequently executed code, or "critical regions." Most previous critical region detectors have been targeted to desktop processors. We introduce a critical region detector targeted to embedded processors, with the unique f... View full abstract»

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  • Code size reduction in heterogeneous-connectivity-based DSPs using instruction set extensions

    Publication Year: 2005, Page(s):1216 - 1226
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB) | HTML iconHTML

    Existing trend of processors shows a progress toward customizable and reconfigurable architectures. In this paper, we study the benefit of combining the architectural design of a VLIW DSP and the concepts of modern customizable processors like ASIPs (application specific instruction set processors) for code size reduction. VLIW DSP architectures exhibit heterogeneous connections between functional... View full abstract»

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  • Distributed data cache designs for clustered VLIW processors

    Publication Year: 2005, Page(s):1227 - 1241
    Cited by:  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1632 KB) | HTML iconHTML

    Wire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the L1 data cache typically remains centralized in What we call partially distributed architectures. However, as ... View full abstract»

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  • Lattice-based memory allocation

    Publication Year: 2005, Page(s):1242 - 1257
    Cited by:  Papers (46)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB) | HTML iconHTML

    We investigate the problem of memory reuse in order to reduce the memory needed to store an array variable. We develop techniques that can lead to smaller memory requirements in the synthesis of dedicated processors or to more effective use by compiled code of software-controlled scratchpad memory. Memory reuse is well-understood for allocating registers to hold scalar variables. Its extension to ... View full abstract»

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  • Automated custom instruction generation for domain-specific processor acceleration

    Publication Year: 2005, Page(s):1258 - 1270
    Cited by:  Papers (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB) | HTML iconHTML

    Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or coprocessors), and the corresponding instructions are added to a baseline processor to meet the critical computational demands of a target application. In this pape... View full abstract»

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  • Some optimizations of hardware multiplication by constant matrices

    Publication Year: 2005, Page(s):1271 - 1282
    Cited by:  Papers (39)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1712 KB) | HTML iconHTML

    This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. ... View full abstract»

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  • FIFO-based multicast scheduling algorithm for virtual output queued packet switches

    Publication Year: 2005, Page(s):1283 - 1297
    Cited by:  Papers (22)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2016 KB) | HTML iconHTML

    Many networking/computing applications require high speed switching for multicast traffic at the switch/router level to save network bandwidth. However, existing queuing-based packet switches and scheduling algorithms cannot perform well under multicast traffic. While the speedup requirement makes the output queued switch difficult to scale, the single input queued switch suffers from head of line... View full abstract»

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  • Concurrent detection of control flow errors by hybrid signature monitoring

    Publication Year: 2005, Page(s):1298 - 1313
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1208 KB) | HTML iconHTML Multimedia Media

    In this paper, we present a new concurrent error-detection scheme by hybrid signature to the online detection of program memory and control flow errors caused by transient and intermittent faults. The proposed hybrid signature-monitoring technique combines the vertical signature with the horizontal signature schemes. We first develop a new vertical signature based on linear additive code whose sig... View full abstract»

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  • Systems support for preemptive disk scheduling

    Publication Year: 2005, Page(s):1314 - 1326
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB) | HTML iconHTML

    Allowing higher-priority requests to preempt ongoing disk IOs is of particular benefit to delay-sensitive and real-time systems. In this paper, we present semi-preemptible IO, which divides disk IO requests into small temporal units of disk commands to improve the preemptibility of disk access. We first lay out main design strategies to allow preemption of each component of a disk access-seek, rot... View full abstract»

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  • [Advertisement]

    Publication Year: 2005, Page(s): 1327
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  • [Advertisement]

    Publication Year: 2005, Page(s): 1328
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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org