By Topic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 7 • Date July 2005

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2005, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (42 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (33 KB)
    Freely Available from IEEE
  • Editorial Appointments for 2005–2006 Term

    Publication Year: 2005, Page(s):773 - 782
    Request permission for commercial reuse | PDF file iconPDF (2245 KB) | HTML iconHTML
    Freely Available from IEEE
  • Optimization techniques for FPGA-based wave-pipelined DSP blocks

    Publication Year: 2005, Page(s):783 - 793
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (498 KB) | HTML iconHTML

    In this paper, techniques for efficient implementation of field-programmable gate-array (FPGA)-based wave-pipelined (WP) multipliers, accumulators, and filters are presented. A comparison of the performance of WP and pipelined systems has been made. Major contributions of this paper are development of an on-chip clock generation scheme which permits finer tuning of the frequency, a synthesis techn... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault tolerance of switch blocks and switch block arrays in FPGA

    Publication Year: 2005, Page(s):794 - 807
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design

    Publication Year: 2005, Page(s):808 - 818
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1743 KB) | HTML iconHTML

    Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can be divided into four categories.. A watermark is a secondary translucent image overlaid into the primary image and appears to a viewer on a careful inspection. The in wa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Global passivity enforcement algorithm for macromodels of interconnect subnetworks characterized by tabulated data

    Publication Year: 2005, Page(s):819 - 832
    Cited by:  Papers (83)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (721 KB) | HTML iconHTML

    With the continually increasing operating frequencies, complex high-speed interconnect and package modules require characterization based on measured/simulated data. Several algorithms were recently suggested for macromodeling such types of data to enable unified transient analysis in the presence of external network elements. One of the critical issues involved here is the passivity violations as... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A source-synchronous double-data-rate parallel optical transceiver IC

    Publication Year: 2005, Page(s):833 - 842
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1959 KB) | HTML iconHTML

    Source-synchronous double-data-rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous DDR optical signaling. On the transmit side, two 8-b electrical inputs are multiplexed, encoded, and sent over two high... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver

    Publication Year: 2005, Page(s):843 - 851
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1107 KB) | HTML iconHTML

    This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing measurement uncertainty in a DSP-based mixed-signal test environment without increasing test time

    Publication Year: 2005, Page(s):852 - 860
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (934 KB) | HTML iconHTML

    Noise, especially clock jitter effects, in a DSP-based mixed-signal test system severely limits its measurement accuracy. This is especially acute in high-frequency sampling systems. This paper illustrates an efficient method to improve measurement accuracy and precision by reducing the uncertainty of a DSP-based measurement without an increase in test time. A new digitizer architecture is introdu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

    Publication Year: 2005, Page(s):861 - 864
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A case study: power and performance improvement of a chip multiprocessor for transaction processing

    Publication Year: 2005, Page(s):865 - 868
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper presents a case study of a different direction, a chip multiprocessor (CMP) with a smaller processor core than a baseline high-end 130-nm 64-bit SPARC server uniprocessor. We demonstrate that the size of the baseline processor core can be reduced b... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Voltage setup problem for embedded systems with multiple voltages

    Publication Year: 2005, Page(s):869 - 872
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    We formulate the following voltage setup problem: how many levels and at which values should voltages be implemented on the system to achieve the maximum energy saving by dynamic voltage scaling (DVS)? This problem challenges whether DVS technique's full potential in energy saving can be reached on multiple voltage systems. In this paper, 1) we derive analytical solutions for dual-voltage system; ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed architectures for parallel long BCH encoders

    Publication Year: 2005, Page(s):872 - 877
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Long Bose-Chaudhuri-Hocquenghen (BCH) codes are used as the outer error correcting codes in the second-generation Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate and codeword length in long-haul optical communication systems. BCH encoders are conv... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A case for asymmetric-cell cache memories

    Publication Year: 2005, Page(s):877 - 881
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB) | HTML iconHTML

    In this paper, we make the case for building high-performance asymmetric-cell caches (ACCs) that employ recently-proposed asymmetric SRAMs to reduce leakage proportionally to the number of resident zero bits. Because ACCs target memory value content (independent of cell activity and access patterns), they complement prior proposals for reducing cache leakage that target memory access characteristi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 882
    Request permission for commercial reuse | PDF file iconPDF (536 KB)
    Freely Available from IEEE
  • Quality without compromise [advertisement]

    Publication Year: 2005, Page(s): 883
    Request permission for commercial reuse | PDF file iconPDF (318 KB)
    Freely Available from IEEE
  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2005, Page(s): 884
    Request permission for commercial reuse | PDF file iconPDF (220 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu