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Semiconductor Manufacturing, IEEE Transactions on

Issue 3 • Date Aug. 2005

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  • Table of contents

    Publication Year: 2005 , Page(s): c1 - c4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2005 , Page(s): c2
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  • Cu Planarization for ULSI Processing by Electrochemical Methods: A Review

    Publication Year: 2005 , Page(s): 341 - 349
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    The planned introduction of porous, low-k dielectric materials into Si-based semiconductor devices will provide substantial challenges for chemical mechanical planarization. These challenges arise primarily from the mechanical fragility of such dielectrics, which may not withstand the force applied during chemical mechanical planarization. Planarization by Cu electropolishing has many advantages, including its noncontact nature, easy endpoint detection, and minimal introduction of contamination. However, pattern sensitivity may limit application of Cu electropolishing to augmenting, rather than completely replacing, chemical mechanical planarization. Electrochemical mechanical planarization appears to have less pattern dependence, but is still an evolving technology whose potential limitations are still unclear. Alternative electrochemical methods for Cu planarization, including electropolishing and electrochemical mechanical planarization are herein reviewed and discussed. View full abstract»

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  • Damage-Less Sputter Depositions by Plasma Charge Trap for Metal Gate Technologies

    Publication Year: 2005 , Page(s): 350 - 354
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    Damage-free sputter deposition process has been developed for metal gate complementary metal-oxide-semiconductor technology. A plasma charge trap (PCT) was introduced in order to eliminate high-energy particle bombardment during sputter deposition processes. Molybdenum (Mo)-gated PMOSFETs were fabricated using a conventional gate-first process. It is shown that the PCT technology yields excellent characteristics in current drivability, as well as in gate oxide integrity (GOI) such as gate leakage current and charge-to-breakdown (Q_BD) . The metal gate was also applied to a nonvolatile memory (NVM), which would require most stringent damage control, and good retention characteristics were demonstrated. View full abstract»

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  • Notching Effect on Metal Etch: A Very Simple Predictive Model

    Publication Year: 2005 , Page(s): 355 - 358
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB) |  | HTML iconHTML  

    In this paper, a very simple model of notching effect is reported. From an engineering point of view, the notching effect is an undercut between bottom of metal strip and stop layer (generally oxide) which can be observed in a  Cl_2 BCl_3 metal etch when the geometry is shrunk. Starting from (Horwitz, 1993), a very detailed relation between geometrical decreasing , ion beam isotropy increasing, and sheath voltage was proposed. Then, a set of experiments performed on patterned aluminum wafers etched in a transformed coupled plasma (TCP) reactor were carried out in order to support the model based on sheath field curvature around metal lines. The experimental results are in good agreement with the theoretical predictions. This confirms the reliability of model proposed in order to manage the engineering problems which take place when a scaling down is performed. View full abstract»

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  • On the Wafer/Pad Friction of Chemical–Mechanical Planarization (CMP) Processes—Part I: Modeling and Analysis

    Publication Year: 2005 , Page(s): 359 - 370
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB)  

    Friction characteristics between the wafer and the polishing pad play an important role in the chemical–mechanical planarization (CMP) process. In this paper, a wafer/pad friction modeling and monitoring scheme for the linear CMP process is presented. Kinematic analysis of the linear CMP system is investigated and a distributed LuGre dynamic friction model is utilized to capture the friction forces generated by the wafer/pad interactions. The frictional torques of both the polisher spindle and the roller systems are used to monitor in situ the changes of the friction coefficient during a CMP process. Effects of pad conditioning and patterned wafer topography on the wafer/pad friction are also analyzed and discussed. The proposed friction modeling and monitoring scheme can be further used for real-time CMP monitoring and process fault diagnosis. View full abstract»

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  • On the Wafer/Pad Friction of Chemical–Mechanical Planarization (CMP) Processes—Part II: Experiments and Applications

    Publication Year: 2005 , Page(s): 371 - 383
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1440 KB)  

    This paper presents the experimental validation and some application examples of the proposed wafer/pad friction models for linear chemical–mechanical planarization (CMP) processes in the companion paper. An experimental setup of a linear CMP polisher is first presented and some polishing processes are then designed for validation of the wafer/pad friction modeling and analysis. The friction torques of both the polisher spindle and roller systems are used to monitor variations of the friction coefficient in situ . Verification of the friction model under various process parameters is presented. Effects of pad conditioning and the wafer film topography on wafer/pad friction are experimentally demonstrated. Finally, several application examples are presented showing the use of the roller motor current measurement for real-time process monitoring and control. View full abstract»

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  • High-Rate Glass Etching Process for Transferring Polycrystalline Silicon Thin-Film Transistors to Flexible Substrates

    Publication Year: 2005 , Page(s): 384 - 389
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    We report on a process technology that makes possible the transfer of polycrystalline silicon thin-film transistor (poly-Si TFT) arrays from an original rigid glass substrate to another flexible plastic substrate. The transfer technology is characterized by its high-rate glass etching process, using a newly developed apparatus. After a description of the transfer sequence free from adhesive contamination, we present experimental observations for high-rate glass etching in hydrofluoric (HF) and hydrochloric (HCl) acid solution mixtures. The etching apparatus provides jets of the solution mixtures to the glass surface in order to achieve good circulation of the solutions in the bath, as well as to remove etch products effectively from the surface. We successfully achieved etch rates as high as 6 \mu m/min with the etched surfaces almost as smooth as the original glass. In order to gain insight into the chemical mechanism of the etching, we developed a simplified kinetic etching model based on a Langmuir isotherm. The model and experimental etch-rate data are generally in good agreement, indicating that the basic modeling approach captures much of the essential chemistry for the high-rate glass etching. The transfer technology allows us to obtain TFT flexible substrates with good electrical characteristics and flexibility even after an annealing process at as high as 150 ^\circ \hbox {C} . These results demonstrate that the transfer technology is a promising candidate for achieving entirely new lightweight electronic devices such as flexible displays and radio frequency identification tags based on TFT flexible substrates. View full abstract»

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  • Online Scheduling of Integrated Single-Wafer Processing Tools With Temporal Constraints

    Publication Year: 2005 , Page(s): 390 - 398
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This paper addresses the issues of online scheduling for integrated single-wafer processing tools with temporal constraints. The integrated single-wafer processing tool is an integrated processing system consisting of single-wafer processing modules and transfer modules. Certain chemical processes require that the wafer flow satisfies temporal constraints, especially, postprocessing residency constraints. This paper proposes an online scheduling method that guarantees both logical and temporal correctness for the integrated single-wafer processing tools. First, mathematical formulation of the scheduling problem using temporal constraint sets is presented. Then, an online, noncyclic scheduling algorithm with polynomial complexity is developed. The proposed scheduling algorithm consists of two subalgorithms: FEASIBLE_SCHED_SPACE and OPTIMAL_SCHED. The former computes the feasible solution space in the continuous time domain, and the latter computes the optimal solution that minimizes the completion time of the last operation of a newly inserted wafer. View full abstract»

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  • Fab Performance

    Publication Year: 2005 , Page(s): 399 - 405
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    To remain competitive and to boost profitability, manufacturers in capital-intensive and highly competitive industries want to maximize throughput and minimize flow time. Achieving high throughput conflicts with achieving low flow time. In order to unhide the tradeoff between throughput and flow time, a performance measure, called manufacturing performance, has been developed. The manufacturing performance is defined by the quotient of the ratio between throughput and flow time of an actual manufacturing system and this ratio of a reference system. The reference system can be adapted by the user in correspondence with objectives. By applying the manufacturing performance to one workstation and using analytic approximations for this workstation, manufacturing performance can be expressed analytically. It seems that manufacturing performance has an optimal value that is given by equipment availability and coefficient of variation. Manufacturing performance is applied also to a four-workstation manufacturing line. Results from analytic approximations show the practicability of the manufacturing performance. Comparison of manufacturing performance with overall fab efficiency, an earlier proposed metric, showed that the manufacturing performance is a more clear metric. This conclusion was based upon simulations with a two-stations manufacturing line. The manufacturing performance is a technical performance metric for manufacturing lines that supports, for instance, economical considerations to obtain optimal throughput-flow time combinations under economical optimal results. This is a useful addition to the existing metrics, which may benefit manufacturers in their operations. The authors consider this contribution as a discussion paper and demand for comment. View full abstract»

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  • Methods to Quantify the Detection Probability of Killing Defects

    Publication Year: 2005 , Page(s): 406 - 411
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    Two methods are presented to quantify the killing defect detection probability, or capture rate, of inline defect inspections. The first method uses yield impact and kill ratio of defects above a given size. By comparing the theoretical, critical-area based dependence between the yield impact and the kill ratio of defects above a given size, with the dependence as found from defect–yield correlation on product wafers, an estimate can be made of the fraction of yield impact explained by detected defects. The second method uses conventional defect–yield correlation. By plotting wafer level yield of clean die against the yield impact found by defect–yield correlation, it is possible to estimate the yield impact of undetected defects. View full abstract»

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  • Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs

    Publication Year: 2005 , Page(s): 412 - 421
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    This paper provides a detailed analysis of the yield of embedded static random access memories (eSRAM) generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design and the physical properties of the layout. A new tool called compiler-based Array Yield Analysis (CAYA) is introduced. CAYA allows for a characterization of the design process which accounts for fault types and the relation between functional and structural faults; moreover, it also relies on a novel empirical model which facilitates yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. Architectural considerations, such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column, and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case. View full abstract»

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  • On the Relationship of Semiconductor Yield and Reliability

    Publication Year: 2005 , Page(s): 422 - 429
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Traditionally, semiconductor reliability has been estimated from the life tests or accelerated stress tests at the completion of manufacturing processes. Recent research, however, has been directed to reliability estimation during the early production stage through a relation model of yield and reliability. Because the relation model depends on the assumed density distribution of manufacturing defects, we investigate the effect of the defect density distributions on the predicted reliability, for a single-area device without repair and for a two-area device with repair, respectively. We show that for any device, reliability functions preserve an ordering of yield functions. It is also pointed out that the repair capability improves only yield but not reliability, resulting in a large value of the factor that scales from yield to reliability. In order to achieve a reliable device, therefore, we suggest to improve yield and to perform the device test such as burn-in if the scaling factor is large. View full abstract»

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  • Semi-Empirical Model-Based Multivariable Iterative Learning Control of an RTP System

    Publication Year: 2005 , Page(s): 430 - 439
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    Comprehensive study on control system design for a rapid thermal processing (RTP) equipment has been conducted with the purpose to obtain maximum temperature uniformity across the wafer surface, while precisely tracking a given reference trajectory. The study covers from model development, identification, optimum multivariable iterative learning control (ILC), to reduced-order controller design. The highlight of the study is the ILC technique on the basis of a semi-empirical dynamic radiation model named as T^4 -model. It was shown that the T^4 -model-based ILC technique can remarkably improve the performance of RTP control compared with the ordinary linear model-based ILC. In addition, reduced-order control methods and the associated optimum sensor location have been addressed. The proposed techniques have been evaluated in an RTP equipment fabricating 8-in wafers. View full abstract»

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  • Online End Point Detection in CMP Using SPRT of Wavelet Decomposed Sensor Data

    Publication Year: 2005 , Page(s): 440 - 447
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    Efficient end point detection (EPD) in chemical mechanical planarization (CMP) is critical to quality and productivity of the wafer fabrication process. The cost of over and under polishing, and the cost of ownership of many expensive metrology-based EPD methods have motivated the researchers to seek cost effective and efficient alternatives. This paper presents a novel method for EPD, which uses a sequential probability ratio test (SPRT) on the wavelet decomposed coefficient of friction (CoF) data from the CMP process. The method is made suitable for online application by developing a moving block data processing strategy, which matches the rate of data acquisition. Tests on both oxide and copper metal CMP show that the developed methodology is uniquely capable of identifying the start and finish of the end point event. View full abstract»

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  • An Initial Intercept Iteratively Adjusted (IIIA) Controller: An Enhanced Double EWMA Feedback Control Scheme

    Publication Year: 2005 , Page(s): 448 - 457
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB) |  | HTML iconHTML  

    The double exponentially weighted moving average (dEWMA) controller is a popular run-to-run controller for a drifted process. It uses the information collected from past process data to adjust the process parameters for the later runs. The dEWMA controller can guarantee long-term stability under suitably fixed discount factors and fairly regular conditions. However, it usually requires a large number of runs to bring the process output to meet its target and, thus, may leave the output out of its specification at the beginning of the first few runs. Hence, dEWMA controller is not suitable for the processes with short production runs. To reduce the possibility of high rework rate, we propose an enhanced dEWMA controller, which we refer to as the initial intercept iteratively adjusted (IIIA) controller, to further eliminate the off-target (nonrandom biases) of the process output. We derive an analytic expression of the process output of the IIIA controller, and present several examples to show that the IIIA reduces the process mean square error significantly, as well as the rework rate. View full abstract»

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  • Locating Disturbances in Semiconductor Manufacturing With Stepwise Regression

    Publication Year: 2005 , Page(s): 458 - 468
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    The ability to locate disturbances in semiconductor manufacturing processes is critical to developing and maintaining a high yield. Analysis of variance (ANOVA), the best current practice for this problem, consists of conducting a series of hypothesis tests at each individual processing step. This approach can lead to excessive false alarms and limited sensitivity when the process contains more than one disturbance. We describe how this problem can be framed as a subset selection problem and propose two new methods based on stepwise regression. Results of over 90 000 Monte Carlo simulations suggest that these new SWR methods locate disturbances with fewer false positives and false negatives than ANOVA. This means process engineers will spend less time responding to false alarms and will be able to locate real disturbances more often. View full abstract»

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  • Correction to “Dynamic Load Balancing Among Multiple Fabrication Lines Through Estimation of Minimum Inter-Operation Time”

    Publication Year: 2005 , Page(s): 469
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  • 2006 International Conference on Microelectronic Test Structures

    Publication Year: 2005 , Page(s): 470
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    Freely Available from IEEE
  • 2005 IEEE International Electron Devices Meeting

    Publication Year: 2005 , Page(s): 471
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    Freely Available from IEEE
  • IEEE International Solid-State Circuits Conference (ISSCC 2006)

    Publication Year: 2005 , Page(s): 472
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    Freely Available from IEEE
  • IEEE Transactions on Semiconductor Manufacturing Information for authors

    Publication Year: 2005 , Page(s): c3
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721