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IEEE Design & Test of Computers

Issue 4 • July-Aug. 2005

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  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • Nanotechnology: Where science of the small meets math of the large

    Publication Year: 2005, Page(s): 289
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    Device integration increased four orders of magnitude over the four decades from the invention of the vacuum tube triode in 1906 to the Eniac machine in 1945. Two intervening world wars also brought the need for solid state radar technologies and US investments into solid-state physics in the 1930s and 1940s. These events directly led to the understanding of defects, semiconductors, band structure... View full abstract»

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  • Table of contents

    Publication Year: 2005, Page(s):290 - 291
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  • Masthead

    Publication Year: 2005, Page(s): 292
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  • IEEE Council for Electronic Design Automation: A new beginning

    Publication Year: 2005, Page(s):293 - 294
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  • Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale

    Publication Year: 2005, Page(s):295 - 297
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (57 KB) | HTML iconHTML

    It is with great pleasure that we introduce this special issue on Advanced Technologies and Reliable Design for Nanotechnology Systems to the IEEE Design & Test readership. We have selected four articles to cover a wide spectrum of techniques and applications for the reliable design of nanoscale systems; the techniques aim to circumvent the high defect rates and transient errors expected in ad... View full abstract»

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  • Recursive TMR: scaling fault tolerance in the nanoscale era

    Publication Year: 2005, Page(s):298 - 305
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    As process technologies decrease in feature size, designers face new reliability challenges. Feature sizes of less than 0.25 μm increase the risk of noise-related faults that result from electrical disturbances in the logic values held in circuits and on wires. Such transient faults can cause single-bit upsets, which in turn can introduce a logical fault in the circuit. In this article, we... View full abstract»

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  • Seven strategies for tolerating highly defective fabrication

    Publication Year: 2005, Page(s):306 - 315
    Cited by:  Papers (73)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    This article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions.... View full abstract»

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  • A reconfiguration-based defect-tolerant design paradigm for nanotechnologies

    Publication Year: 2005, Page(s):316 - 326
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    This article discusses a novel probabilistic design paradigm targeting reconfigurable architected nanofabrics and points to a promising foundation for comprehensively addressing, at the system level, the density, scalability, and reliability challenges of emerging nanotechnologies. The approach exposes a new class of yield, delay, and cost trade-offs that must be jointly considered when designing ... View full abstract»

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  • Computer Society Information

    Publication Year: 2005, Page(s): 327
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  • Toward hardware-redundant, fault-tolerant logic for nanoelectronics

    Publication Year: 2005, Page(s):328 - 339
    Cited by:  Papers (75)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage mu... View full abstract»

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  • New ECC for crosstalk impact minimization

    Publication Year: 2005, Page(s):340 - 348
    Cited by:  Papers (30)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Signal integrity in high-speed bus designs is put at risk by crosstalk-related bus delays. This article provides a comprehensive study of the usefulness of error correcting code (ECC) redundancy in reducing such delays. It shows that Dual Rail codes perform better at this task than Hamming codes. We describe the modification of DR code that offers some distinct advantages. View full abstract»

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  • Precis: a usercentric word-length optimization tool

    Publication Year: 2005, Page(s):349 - 361
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Translating an algorithm designed for a general-purpose processor into an algorithm optimized for custom logic requires extensive knowledge of the algorithm and the target hardware. Precis lets designers analyze the precision requirements of algorithms specified in Matlab. The design time tool combines simulation, user input, and program analysis to help designers focus their manual precision opti... View full abstract»

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  • Soft-spot analysis: targeting compound noise effects in nanometer circuits

    Publication Year: 2005, Page(s):362 - 375
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Soft-spot analysis identifies regions in a circuit that are most susceptible to multiple noise sources and their compound effects so that designers can harden those spots for greater robustness. HSpice simulation validates the methodology's quality, and demonstration on a commercial embedded processor shows its scalability. View full abstract»

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  • Modeling and analysis of parametric yield under power and performance constraints

    Publication Year: 2005, Page(s):376 - 385
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits... View full abstract»

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  • BIST the hard way

    Publication Year: 2005, Page(s):386 - 387
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  • Adding value to design and test through education: What are the challenges?

    Publication Year: 2005, Page(s): 388
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    THE 6TH IEEE Latin American Test Workshop (LATW 05), took place from 30 March to 2 April 2005 in Salvador, Brazil. The workshop included a panel discussion on the challenges for modern design and test education, which attracted much attention from the audience. View full abstract»

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  • Conference Reports

    Publication Year: 2005, Page(s):389 - 390
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    Design, Automation and Test in Europe Norbert Wehn, general chair, DATE 2005 Georges Gielen, general chair, DATE 2006 DATE, Europe's premier conference and exhibition for electronic design, automation, and test, took place in Munich, from 7 to 11 March 2005. More than 4,700 people attended this event--a record turnout. The conference included 234 technical presentations selected from a record 825 ... View full abstract»

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  • Design Automation Technical Committee Newsletter

    Publication Year: 2005, Page(s): 391
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  • What's the problem?

    Publication Year: 2005, Page(s): 392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB) | HTML iconHTML

    Most readers of IEEE Design & Test are IC people. We IC people have been running scared our entire careers. On the test side, at least, we've been sure that the next process node, the next tenfold increase in gate and transistor count, will break our tools and create a set of defects that we don't know how to test. Disaster is always just around the corner. We hope that new techniques, like ID... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty