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IEE Proceedings - Computers and Digital Techniques

Issue 4 • Date 8 July 2005

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Displaying Results 1 - 9 of 9
  • Exploiting temporal loads for low latency and high bandwidth memory

    Publication Year: 2005, Page(s):457 - 466
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (314 KB)

    Increasing clock frequencies and issue rates aggravates the memory latency problem, imposing higher memory bandwidth requirements. While caches can be multi-ported to provide high memory bandwidth, the increase in access latency with the increase in the number of ports limits their potential. The paper proposes a novel technique, called the 'temporal load cache architecture', to reduce load latenc... View full abstract»

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  • Topology adaptive network-on-chip design and implementation

    Publication Year: 2005, Page(s):467 - 472
    Cited by:  Papers (18)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (472 KB)

    Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is propos... View full abstract»

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  • Focalising dynamic value prediction to CPU's context

    Publication Year: 2005, Page(s):473 - 481
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (522 KB)

    Value prediction (VP) is a relatively new technique that increases performance by eliminating true data dependency constraints. VP architectures allow data dependent instructions to issue and execute speculatively using the predicted value. This technique is built on the concept of value locality, which describes the likelihood of a previously seen value recurring within a storage location. The au... View full abstract»

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  • Low-power branch target buffer for application-specific embedded processors

    Publication Year: 2005, Page(s):482 - 488
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (161 KB)

    A methodology for a low-power branch identification mechanism which enables the design of extremely power-efficient branch predictors for embedded processors is presented. The proposed technique utilises application-specific information regarding the control-flow structure of the program's major loops. Such information is used to completely eliminate the power hungry branch target buffer (BTB) loo... View full abstract»

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  • Efficient unified Montgomery inversion with multibit shifting

    Publication Year: 2005, Page(s):489 - 498
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (241 KB)

    Computation of multiplicative inverses in finite fields GF(p) and GF(2n) is the most time-consuming operation in elliptic curve cryptography, especially when affine co-ordinates are used. Since the existing algorithms based on the extended Euclidean algorithm do not permit a fast software implementation, projective co-ordinates, which eliminate almost all of the inversion operations fro... View full abstract»

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  • Low-power variable-length fast Fourier transform processor

    Publication Year: 2005, Page(s):499 - 506
    Cited by:  Papers (34)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (293 KB)

    Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path d... View full abstract»

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  • Selective block buffering TLB system for embedded processors

    Publication Year: 2005, Page(s):507 - 516
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (539 KB)

    The authors present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the tag buffer. Dynamic power savings are achieved by reducing the numb... View full abstract»

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  • Zero-overhead loop controller that implements multimedia algorithms

    Publication Year: 2005, Page(s):517 - 526
    Cited by:  Papers (4)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (157 KB)

    Multimedia algorithms generally consist of regular repetitive loop constructs. The authors present a novel control unit design for implementing such loop intensive algorithms. The proposed architecture, termed a zero-overhead loop controller (ZOLC) exploits the regularity of computations, which is a common characteristic of multimedia algorithms, in order to efficiently support the corresponding d... View full abstract»

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  • Signature-monitoring technique based on instruction-bit grouping

    Publication Year: 2005, Page(s):527 - 536
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (241 KB)

    A new concurrent error-detection scheme monitors the signatures in online detection of instruction memory and control flow errors caused by transient and intermittent faults. The proposed signature-monitoring technique is based on the grouping of column bit information of instructions in a block to produce the block signature. The grouping size that represents the number of bits in a group could a... View full abstract»

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