By Topic

Electron Device Letters, IEEE

Issue 7 • Date July 1991

Filter Results

Displaying Results 1 - 13 of 13
  • Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy

    Publication Year: 1991 , Page(s): 357 - 359
    Cited by:  Papers (26)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB)  

    High-quality SiGe heterojunction bipolar transistors (HBTs) have been fabricated using material grown by molecular beam epitaxy (MBE). The height of parasitic barriers in the conduction band varied over the wafer, and the influence of these barriers on controller current, early voltage, and cutoff frequency were studied by experiments and simulations. Temperature-dependent measurements were performed to study the influence of the barriers on the effective bandgap narrowing in the base and to obtain an expression for the collector-current enhancement. From temperature-dependent measurements, the authors demonstrate that the collector-current enhancement of the HBTs can be described by a single exponential function with a temperature-independent prefactor.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The influence of gate-feeder/mesa-edge contacting on sidegating effects in In/sub 0.52/Al/sub 0.48/ As/In/sub 0.53/Ga/sub 0.47/As heterostructure FET's

    Publication Year: 1991 , Page(s): 360 - 362
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (287 KB)  

    Sidegating effects in InAlAs/InGaAs heterostructure field effect transistors (HFETs) were experimentally investigated. Two different configurations of gate feeder across the mesa edges are compared in In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As. HFETs. HEMTs and heterostructure insulated-gate FETs (HIGFETs) were fabricated, each with different gate-feeder configurations. HFETs with the gate air bridge over the mesa edge can maintain 99% of the drain-source (I/sub ds/) current level at sidegate voltages (V/sub sg/) extending up to -30 V, while the non-air-bridge configuration of HFETs show a 30% drop of I/sub ds/ at the same V /sub sg/. This significant discrepancy of sidegating effect is attributed to depletion region modulation at the mesa edge below the gate feeder. By lifting the gate feeder above the mesa step, sidegating is reduced, which suggests the channel/substrate trap effects are negligibly small. The role of air-bridge structures in determining the sidegating characteristics is discussed.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The influence of gate edge shape on the degradation in hot-carrier stressing of n-channel transistors

    Publication Year: 1991 , Page(s): 363 - 365
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    The hot-carrier properties of planar and graded gate structures (upturning of the gate edge in the gate overlap region) of n-MOS transistors were examined. It was found that the type of degradation suffered by each type of device depends on the shape of the gate edge. This is interpreted in terms of the degree of gate control of the gate over the region in which the damage takes place in the different devices. The nongraded gate (NGG) devices degrade chiefly by a V/sub t/ shift, whereas the graded gate (GG) devices show a pronounced transconductance decay, with practically no V/sub t/ shift. It is suggested that the damage is situated in the gate overlap region, and that the different degradations result from a weaker field control of the gate over the degraded region leading to a series resistance type of effect in the case of the GG structure. This is supported by two-dimensional simulations.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement

    Publication Year: 1991 , Page(s): 366 - 368
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB)  

    The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2- mu m effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • InP/InGaAs double-heterojunction bipolar transistors grown on [100] Si by metalorganic chemical vapor deposition

    Publication Year: 1991 , Page(s): 369 - 371
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The authors report the successful fabrication of InP/InGaAs double-heterojunction bipolar transistors (DHBTs) grown by metalorganic chemical vapor deposition (MOCVD) on Si substrates. The Si substrates used were p-type (boron doped) FZ grown wafers with a resistivity of 5000 Omega *cm, oriented 2 degrees off the [100] plane toward the [110] direction. Epitaxial layers for DHBTs were grown on the Si substrate with a thin GaAs buffer layer. A two-step growth process was applied for the InP layers on GaAs-on-Si wafers. The transistors exhibit high current gains over 200, which is comparable to those in transistors grown on InP substrates. The dislocations are found to increase the recombination current very little in the neutral base region, but increase in generation-recombination current at the emitter-base interface.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A latch phenomenon in buried N-body SOI NMOSFET's

    Publication Year: 1991 , Page(s): 372 - 374
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB)  

    The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V/sub GS/ is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of LDD devices for cryogenic operation

    Publication Year: 1991 , Page(s): 375 - 378
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Picosecond optoelectronic gating of silicon bipolar transistors by locally integrated GaAs photoconductive devices

    Publication Year: 1991 , Page(s): 379 - 381
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    Integration of picosecond GaAs photoconductive devices with silicon bipolar transistors to provide a high-performance optoelectronic gating element is demonstrated. GaAs photoconductive circuit elements (PCEs) with approximately 15-ps FWHM photocurrent transient responses have been integrated in base-drive circuit configurations. Results have demonstrated that approximately 70-ps FWHM pulses of >1 mA (5 V switching across 5 k Omega ) are possible using approximately 3-4 pJ of optical input at 820 nm. Furthermore, for the silicon bipolar transistor process which has a nominal f/sub t/ > 10 GHz, gating pulses with approximately 50-ps rise times, limited by the input optical pulse, have been observed.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Millimeter-wave AlGaAs/GaAs p-n-p HBT

    Publication Year: 1991 , Page(s): 382 - 384
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    The total emitter-to-collector delay for a p-n-p AlGaAs/GaAs heterojunction bipolar transistor (HBT) has been reduced to 5.7 ps by extending the cutoff frequency for these devices to the millimeter-wave range. A total charging delay of 1.2 ps was obtained by a lightly doped emitter and by reducing the collector resistance. Low transit delays totaling 4.5 ps were achieved with a thin (440 AA) uniformly doped base and a thin (2800 AA) collector. The reduction in these delays permitted a non-self-aligned (1- mu m emitter mesa/base contact separation) device with two emitters (2.6*10 mu m/sup 2/ each) and a single base contact to exhibit an f/sub t/ of 28 GHz.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Molecular beam epitaxial GaAs/Al/sub 0.2/Ga/sub 0.8/As p-channel field-effect transistors on

    Publication Year: 1991 , Page(s): 385 - 386
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (221 KB)  

    P-channel and n-channel heterostructure field effect transistors (HFETs) have been simultaneously fabricated by one-step molecular beam epitaxial growth of Si-doped Al/sub 0.2/Ga/sub 0.8/As/GaAs heterostructures on patterned View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-voltage current saturation in emitter switched thyristors

    Publication Year: 1991 , Page(s): 387 - 389
    Cited by:  Papers (21)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    Current saturation at high voltages in MOS-gated emitter switched thyristors (ESTs) is demonstrated. It is shown that by using an improved EST structure containing a dual-channel lateral MOSFET, the thyristor current can be saturated to high voltages through MOS gate control. In experimental devices with 600-V forward blocking capability, it is observed that current densities of 110 A/cm/sup 2/ could be saturated up to 450 V with a gate bias of 3.5 V. Experimental measurements and numerical simulations indicate that, during current saturation, the voltage appears across the junction between the P-base region and the N/sup -/ drift region and not across the lateral MOSFET.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-temperature polysilicon TFT with gate oxide grown by high-pressure oxidation

    Publication Year: 1991 , Page(s): 390 - 392
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB)  

    Polysilicon thin-film transistors (TFTs) were fabricated with the maximum processing temperature limited to 650 degrees C. Best results were obtained when the gate oxide was grown by a two-step high-pressure oxidation process, using high-pressure steam and then dry oxygen both at 15 atm and 650 degrees C. The TFTs exhibit a mobility of 34 cm/sup 2//V*s, threshold voltage of 3.5 V, leakage current below 0.01 pA/ mu m, subthreshold slope of 0.18 V/decade, and an ON/OFF ratio of over eight orders of magnitude. These values are comparable to those obtained with conventional polysilicon TFTs using high-temperature thermal oxidation.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new technique for measuring lateral distribution of oxide charge and interface traps near MOSFET junctions

    Publication Year: 1991 , Page(s): 393 - 395
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A technique to measure the lateral distribution of both interface traps and trapped oxide charge near the source-drain junctions in MOSFETs is presented. Its basic principle is described. This technique derives from the charge-pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Examples are shown for hot-carrier stressed MOS transistors.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee