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IEE Proceedings - Circuits, Devices and Systems

Issue 3 • Date 3 June 2005

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Displaying Results 1 - 12 of 12
  • Charge transport in organic and polymer thin-film transistors: recent issues

    Publication Year: 2005, Page(s):189 - 209
    Cited by:  Papers (24)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2034 KB)

    Interest in organic and polymer thin film transistors (OTFTs and PTFTs; hereafter both are called PTFTs) has grown rapidly in the last decade. However, the theory of charge transport in PTFTs lags experiments, so it is difficult to provide the required feedback to device designers and technologists. Therefore, the authors present an analysis of charge transport in PTFTs. It is based on extensive p... View full abstract»

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  • High-speed multi-input comparator

    Publication Year: 2005, Page(s):210 - 214
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1353 KB)

    A comparison cell is presented that is able to compare n-data at a time and is based on dynamic logic methodology. The results of the n-data are sent to an m-bit NAND gate for the m×n comparison, where m corresponds to the word length of each datum. Compared to conventional comparators the proposed comparator requires fewer transistors and the circuit delay time is also shortened. To verify ... View full abstract»

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  • Fault characterisation and testability issues of complementary pass transistor logic circuits

    Publication Year: 2005, Page(s):215 - 222
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1267 KB)

    Testability of basic and complex logic gates employing complementary pass transistor logic (CPL) circuits under various single stuck faults has been investigated. Results show that all stuck-on faults, bridging faults and more than 90% of stuck-at faults in basic CPL gates are detectable only by current monitoring, generally known as IDDQ testing. It is also shown that all stuck-open fa... View full abstract»

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  • Low power and fast system wakeup circuit

    Publication Year: 2005, Page(s):223 - 228
    Cited by:  Papers (2)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1563 KB)

    The authors describe a low-voltage, low-power, fast system wakeup circuit, with no requirement for an external component in the RC oscillator. The wakeup circuit includes a POR (power-on-reset) circuit to detect the status of the power supply (VCC), a constant Gm bias circuit to bias the ring RC-oscillator, and a clock control unit to ensure stable clock frequency output. The... View full abstract»

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  • Programmable gain amplifier with colour balancing for CCD image sensors

    Publication Year: 2005, Page(s):229 - 235
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (4663 KB)

    The authors present a new programmable gain amplifier (PGA) with colour balancing for single-chip CCD colour image sensors. The PGA with synchronised gain switching allows higher SNR to be achieved in the amplified image while maintaining sufficient gain resolution and low power dissipation. A floating-point expression is used in the designed five-stage pipelined PGA for compact and low-power impl... View full abstract»

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  • Accelerating matrix product on reconfigurable hardware for image processing applications

    Publication Year: 2005, Page(s):236 - 246
    Cited by:  Papers (9)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (4823 KB)

    Matrix multiplication is very important in many types of applications, including image and signal processing. The suitability of reconfigurable hardware devices, in the form of field programmable gate arrays (FPGAs), is investigated as a low-cost solution for implementing two matrix multipliers for 3D affine transformations and colour space conversion. A first solution based on processing large ma... View full abstract»

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  • Design and realisation of a new hardware efficient IP core for the 1-D discrete Fourier transform

    Publication Year: 2005, Page(s):247 - 258
    Cited by:  Papers (1)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1677 KB)

    The authors present a new hardware efficient design approach and the associated intellectual property (IP) core design for a one-dimensional (1-D) discrete Fourier transform (DFT). They optimise the proposed DFT design, at both the algorithmic and architectural levels, to provide low hardware cost. At the algorithmic level, first a radix-2c algorithm is used to split a 1-D length-N DFT ... View full abstract»

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  • Baseband predistorter using direct spline computation

    Publication Year: 2005, Page(s):259 - 265
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1841 KB)

    A baseband predistorter is presented. Key features of the predistorter reside in the use of cubic spline interpolation to generate predistorted input data to the power amplifier, without the time convergence problems of classical approaches, with the goal of a reduction in the computational effort. Simulated behaviour of the proposed scheme is presented, demonstrating the effectiveness of the appr... View full abstract»

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  • Variable sampling window flip-flops for low-power high-speed VLSI

    Publication Year: 2005, Page(s):266 - 271
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1690 KB)

    The authors describe novel flip-flops with improved robustness and reduced power consumption. The variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces internal power consumption for high input switching activities. The clock swing-reduced variable sampling... View full abstract»

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  • Design and implementation of electrical-supply-free VLSI circuits

    Publication Year: 2005, Page(s):272 - 278
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1719 KB)

    The authors propose an approach to the design and implementation of VLSI circuits free of electrical supply and power rails. With this approach, the circuits can be made to use the power carried by the incident light for supply, control and optical charge pumping. The proposed basic cell consists of an NMOS transistor and a photodiode connected between the drain of the transistor and the ground. T... View full abstract»

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  • Decoupling technique for CMOS gate with strong-coupled components

    Publication Year: 2005, Page(s):279 - 286
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1333 KB)

    A novel decoupling technique for a CMOS gate with strong-coupled components is presented. The feedback structure is reduced to a unidirectional one. The hysteresis phenomena are characterised. Using the waveform relaxation technique, the decoupling principle and procedures are discussed in detail. The model predictions are verified by SPICE simulation. View full abstract»

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  • 10-bit switched-current digital-to-analogue converter

    Publication Year: 2005, Page(s):287 - 290
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1273 KB)

    The design of a 10-bit switched-current digital-to-analogue (D/A) converter is presented. A combined-input algorithm is adopted to reduce both architecture and power dissipation. The proposed D/A converter is implemented with a standard 0.35 μm CMOS process technology. The chip occupies an area of 0.35 mm2 and consumes a small power of 26.1 mW with speed up to 31.25 Msamples/s. View full abstract»

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