IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Aug. 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Engineering change protocols for behavioral and system synthesis

    Publication Year: 2005, Page(s):1145 - 1155
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    Rapid prototyping and development of in-circuit and FPGA-based emulators as key accelerators for fast time-to-market has resulted in a need for efficient error correction mechanisms. Fabricated or emulated prototypes upon error diagnosis require an effective engineering change (EC). We introduce a novel design methodology which consists of pre- and post-processing techniques that enable EC with mi... View full abstract»

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  • Weibull-based analytical waveform model

    Publication Year: 2005, Page(s):1156 - 1168
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    Current complimentary metal-oxide-semiconductor technologies are characterized by interconnect lines with increased relative resistance with respect to driver output resistance. Designs generate signal waveshapes that are very difficult to model using a single-parameter model such as the transition time. In this paper, we present a simple and robust two-parameter analytical expression for waveform... View full abstract»

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  • Compressible area fill synthesis

    Publication Year: 2005, Page(s):1169 - 1187
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB) | HTML iconHTML

    Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low-k dielectrics. To improve manufacturability, and in particular to enable more uniform chemical-mechanical planarization (CMP), it is necessary to insert area fill features into low-density layout regions. Because area fil... View full abstract»

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  • Multilevel fixed-point-addition-based VLSI placement

    Publication Year: 2005, Page(s):1188 - 1203
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    A placement problem can be formulated as a quadratic program with nonlinear constraints. Those constraints make the problem hard. Omitting the constraints and solving the unconstrained problem results in a placement with substantial cell overlaps. To remove the overlaps, we introduce fixed points into the nonconstrained quadratic-programming formulation. Acting as pseudocells at fixed locations, t... View full abstract»

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  • Power grid analysis using random walks

    Publication Year: 2005, Page(s):1204 - 1224
    Cited by:  Papers (79)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    This paper presents a class of power grid analyzers based on a random-walk technique. A generic algorithm is first demonstrated for dc analysis, with linear runtime and the desirable property of localizing computation. Next, by combining this generic analyzer with a divide-and-conquer strategy, a single-level hierarchical method is built and extended to multilevel and "virtual-layer" hierarchy. Ex... View full abstract»

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  • An efficient and robust method for ring-oscillator simulation using the harmonic-balance method

    Publication Year: 2005, Page(s):1225 - 1233
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    A novel approach for simulating the periodic steady state of ring oscillators with the harmonic-balance method is described. This approach is efficient and robust compared with traditional approaches. The key idea exploited is the structure of the ring oscillator, in which the properties of a single delay cell are used to simulate the response of the overall oscillator. The proposed method yields ... View full abstract»

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  • Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level

    Publication Year: 2005, Page(s):1234 - 1240
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    Maintaining coverage with increasing circuit scale has become a critical problem for logic-verification processes. While transaction-level verification (TLV) is an important step forward, fine-grained (FG) TLV provides better signal-level coverage by reactively changing transactors instead of transaction-level scenarios. Evaluations with a microprocessor design show the effectiveness of FGTLV; all... View full abstract»

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  • Hierarchical approach to exact symbolic analysis of large analog circuits

    Publication Year: 2005, Page(s):1241 - 1250
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing symbolic product terms. But instead of constructing DDD graphs directly from a flat circuit matrix, the new method constructs DDD graphs in a hierarchical way based on hierarchically defined circuit structures. The resulting... View full abstract»

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  • A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures

    Publication Year: 2005, Page(s):1250 - 1261
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    An overview of standard macromodeling techniques (i.e., employ poles but no phase shifts) for transient simulation of high-speed interconnects is first presented. Then, the limitations of these standard macromodeling techniques (e.g., high model order and slow convergence) are discussed. In order to overcome these limitations, generalized method of characteristics (MoC) techniques include the phys... View full abstract»

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  • Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models

    Publication Year: 2005, Page(s):1261 - 1271
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    As SystemC gains popularity as a modeling language of choice for system-on-chip (SoC) designs, heterogeneous modeling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a nondeterministic discrete-event (DE) simulation kernel that schedules events at run time mimicking other models of computa... View full abstract»

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  • On fault equivalence, fault dominance, and incompletely specified test sets

    Publication Year: 2005, Page(s):1271 - 1274
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    It is shown that fault equivalence and fault dominance relations defined based on the sets of completely specified test vectors that detect each fault may not hold when incompletely specified test vectors are used together with three-value simulation. Experimental results are presented to demonstrate the extent of this phenomenon. Its effects are discussed in general and in the context of a specif... View full abstract»

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  • Worst case crosstalk noise for nonswitching victims in high-speed buses

    Publication Year: 2005, Page(s):1275 - 1283
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    Considering a RLC interconnect model, we determine switching patterns and switching times of multiple aggressors to generate the worst case crosstalk noise (WCN) for a quiet or a noisy victim. We consider the routing direction as it has a significant impact under the RLC model. When there are no timing window constraints, we show that the commonly used superposition algorithm results in 15% undere... View full abstract»

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  • A provably passive and cost-efficient model for inductive interconnects

    Publication Year: 2005, Page(s):1283 - 1294
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    To reduce the model complexity for inductive interconnects, the vector potential equivalent circuit (VPEC) model was introduced recently and a localized VPEC model was developed based on geometry integration. In this paper, the authors show that the localized VPEC model is not accurate for interconnects with nontrivial sizes. They derive an accurate VPEC model by inverting the inductance matrix un... View full abstract»

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  • Sequential circuit ATPG using combinational algorithms

    Publication Year: 2005, Page(s):1294 - 1310
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    In this paper, we introduce two design-for-testability (DFT) techniques based on clock partitioning and clock freezing to ease the test generation process for sequential circuits. In the first DFT technique, a circuit is mapped into overlapping pipelines by selectively freezing different sets of registers so that all feedback loops are temporarily cut. An opportunistic algorithm takes advantage of... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 1311
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  • Explore IEL IEEE's most comprehensive resource

    Publication Year: 2005, Page(s): 1312
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu