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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 1987

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Displaying Results 1 - 25 of 31
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
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  • Surface potential effect on gate—Drain avalanche breakdown in GaAs MESFET's

    Page(s): 2027 - 2033
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    The surface potential effect on gate-drain avalanche breakdown in GaAs MESFET's is investigated with a two-dimensional device simulator. It is shown that the surface potential effect changes the potential distribution in GaAs MESFET's drastically and therefore plays an important role in determining drain breakdown voltage. In addition, two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, are analyzed. View full abstract»

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  • GaAs MESFET simulation using PISCES with field-dependent mobility-diffusivity relation

    Page(s): 2034 - 2039
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    Most conventional semiconductor device simulators, such as PISCES and BAMBI, use a constant diffusivity-to-mobility ratio modeling (linear relation). We modify PISCES to perform field-dependent diffusivity-to-mobility ratio (nonlinear relation) GaAs MESFET simulation and compare it to the constant ratio linear modeling. The results show that current overshoot and stable Gunn-domain formation occurred at a lower channel-impurity concentration for the field-dependent diffusivity-to-mobility ratio case. The transconductance and threshold voltage of a 1-µm gate-length MESFET are compared also. View full abstract»

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  • Band offset effect on transport in AlxGa1-xAs/GaAs heterojunction bipolar transistors grown by metalorganic chemical vapor deposition

    Page(s): 2040 - 2042
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    AlxGa1-xAs/GaAs heterojunction bipolar transistors were grown with x in the emitter from 0 to 0.57 and the band offset effect on electron transport has been studied using a new technique. The data, though preliminary, indicate that the transport is dominated by electrons near the conduction-band minima when x < 0.45, but not when x = 0.57. View full abstract»

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  • Planar monolithic integration of LED and FET devices on a conductive substrate

    Page(s): 2043 - 2048
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    This paper describes results of a study on the monolithic integration of AlGaAs light-emitting diodes with GaAs field-effect transistors on a conductive p-GaAs substrate. Using a selective growth technique, a horizontal configuration is fabricated that allows separate optimization of the two types of devices and provides a quasi-planar surface. This approach is compatible with the standard GaAs integrated-circuit technology. By inserting an undoped layer and a p-n junction between the active layer of the FET and the substrate leakage currents below 500 µA for bias voltage up to 9 V are obtained for these insulation structures. The emitted light intensity of the LED, connected in series with the FET, exhibits a nearly linear dependence on the driving gate potential. Temperature or optical crosstalk effects were not observed. Fall and rise times around 20 ns were measured from the pulse response characteristics. This switching time is limited by the LED whereas the FET and isolation layers were found not to affect the switching behavior of the circuit in this time frame. View full abstract»

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  • A supervised simulation system for process and device designs based on a geometrical data interface

    Page(s): 2049 - 2058
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    A supervised simulation system for two-dimensional simulation has been developed covering the range from pattern layout to process simulation and also to device simulation. The system features a system controller for module programs, and the feasibility of module programs based on an intermediate topography data format with which data go between the module programs. The system controller can automatically generate appropriate jobs, assigning pertinent input data. The topography data acts as an interface through process simulation and up to device simulation. The system will eliminate laborious work for designers and greatly reduce the time required for process and device designs. View full abstract»

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  • Three-dimensional analytical simulation of self- and cross-responsivities of photovoltaic detector arrays

    Page(s): 2059 - 2070
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    Decreasing dimensions, along with an increasing number of elements in imaging photodiode arrays, result in the degradation of spatial resolution and sensitivity due to lateral transport. This effect is modeled using a novel 3-D analytical solution of the continuity equation. The model enables the full 3-D analysis of lateral transport as manifested in excess carrier distribution, photocurrent, and self- and cross-responsivities. Three detector structures are investigated: the semi-infinite substrate, the perfectly collecting, and the perfectly reflecting backside. The front and rear illuminations are treated. The calculated results for the 3-D case deviate fundamentally from those predicted by the 1-D model. The 3-D model succeeds in explaining the reduced quantum efficiency of small-area detectors. It also predicts the limited effect diffusion length has on self-responsivity and cut-off wavelength. The calculated spectral responses fit extremely well data measured on InSb and HgCdTe test arrays. As a powerful design tool, the model enables optimizing responsivity and crosstalk by varying element geometry and spacing, optical aperture, lifetime, and spectral range. The model can be applied to any semiconductor photodiode array provided the relevant physical and geometrical parameters are known. View full abstract»

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  • Two-frequency drive for AC-refresh plasma display panels

    Page(s): 2071 - 2076
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    A new drive scheme, with mixed low- and high-frequency drives, has been developed for large-capacity (large number of dots) ac-refresh plasma display panels. Its usefulness for suppressing both firing-voltage increase and luminance-level decrease in a large-capacity panel was confirmed using a practical-size plasma panel. This drive technique can produce a large display panel ( > 400-600 scan lines) with about 50-percent lower power dissipation and higher luminance level than a conventional drive technique. It has been clarified experimentally that these results are due to the sufficient formation of the wall charge at an initial discharge period. View full abstract»

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  • Carrier transport in semiconductor detectors of magnetic domains

    Page(s): 2077 - 2085
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    Carrier transport in Hall-type devices detecting magnetic domains is analyzed in terms of a two-dimensional numerical model, using a finite element scheme. The numerical model allows the calculation of magnetic sensitivity for general device geometries or structures, any homogeneous semiconductor material, and arbitrary domain shapes and sizes. We specifically consider three types of commonly used Hall detectors: the conventional Hall plate, the split-electrode Hall device, and the Hall cross. The magnetic sensitivity for these devices is computed for various domain configurations. In particular, the device's output response for moving domains is investigated and appropriate figures of merit are established with respect to spatial resolution. A comparison of the numerical solutions with previously reported experimental results supports the validity of our analysis. View full abstract»

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  • A dual-mechanism solid-state carbon-monoxide and hydrogen sensor utilizing an ultrathin layer of palladium

    Page(s): 2086 - 2097
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    Pd-gate MOS sensors were fabricated on p-type silicon wafers. The gate films were 25 and 40 Å thick with an oxide thickness of 100 Å. Contacts were made to allow measurement of the MOS capacitance and of the impedance across the gate film. Voltage shifts in the MOS C-V curves and shifts in the Pd film impedance were measured as functions of 1) the concentration of CO and H2; 2) time as the gas ambient was varied. The devices showed sensitivity to H2at room temperature and to CO and H2at elevated temperatures. When the 25-Å device was exposed to 300 ppm H2in air at room temperature, the C-V curve shifted by -430 mV and the impedance decreased by 20 ω or 5 percent. When the 25-Å device was exposed to 5000 ppm CO in air at 150°C, the C-V curve shifted - 200 mV and the impedance decreased by 140 ω (10 percent). When exposed to 0.1-percent H2in argon, the resistance of the 40-Å device increased by about 2 percent. When measured as a function of time, the changes in MOS capacitance tend to track the changes in impedance. An effect similar to hydrogen-induced drift (HID) was observed for CO at elevated temperature. View full abstract»

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  • Mathematical modeling of photoconductor transient response

    Page(s): 2098 - 2107
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    We present a Photoconductor device model that is based on time-dependent convective/diffusive continuity and transport equations. Electron and hole trapping on deep-level impurities is accounted for by trapping-kinetics rate equations. The coupling between carrier drift and electric field is completed through Poisson's equation. The system of model equations is solved numerically with boundary conditions that represent ideal ohmic contacts. Computed results are presented for different photoconductor lengths and bias voltages with spatially uniform, rectangular light-pulse excitation. Material parameters appropriate for iron-doped indium phosphide are used. View full abstract»

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  • Self-aligned cobalt disilicide for gate and interconnection and contacts to shallow junctions

    Page(s): 2108 - 2115
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    In this paper we present a new gate and interconnection and contact metallization technology that uses cobalt disilicide for both purposes. Cobalt disilicide, with a thin polycrystalline film resistivity of 15-20 µ Ω .cm, offers a 0.5-1-Ω/ sheet resistance at the gate level in the popular silicide/polysilicon gate metal scheme. It also offers an excellent contact metallization scheme to shallow junctions. This paper describes a scheme that utilizes self-aligned patterning features and low-temperature processing and shows stability up to 900°C. Various other features of the processing and characteristics of the silicide are also presented. View full abstract»

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  • Design criteria for Si point-contact concentrator solar cells

    Page(s): 2116 - 2123
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    Design criteria for concentrator solar cells are presented for the highly three-dimensional case of backside point-contact solar cells. A recent new experimental result, a 28-percent efficient cell (25°C, 15-W/cm2incident power) is used as a case study of the dependences of the recombination components and the carrier density gradients on the geometrical design parameters. The optimum geometry is found to depend upon the intended design power density as well as the attainable physical parameters allowed by the fabrication techniques utilized. Modeling projections indicate that an ultimate efficiency of 30.6 percent (36 W/cm2, 300 K) is achievable using the diffused emitters presently employed on these cells. Incorporation of results from the study of polycrystalline emitters could improve these efficiencies toward 31.7 percent. View full abstract»

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  • Electrical characteristics of MOSFET's utilizing Oxygen—Argon sputter-deposited gate Oxide films

    Page(s): 2124 - 2128
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    This paper presents a detailed look at the electrical characteristics of MOSFET's utilizing oxygen-argon sputter-deposited gate-oxide films for low-temperature MOSFET fabrication. The gate-oxide films are deposited at low temperature (200°C) by oxygen-argon sputtering of an SiO2target. The MOSFET's so formed are confirmed to have triode characteristics. Moreover, oxygen mixing makes it possible to considerably improve the MOSFET field-effect mobility and subthreshold slope over those of argon-only sputter-deposited film to 700 cm2/V's and 170 mV/decade. These improvements are found to be caused by the remarkable reduction in surface-state density. These results confirm the usefulness of oxygen-argon sputter-deposited gate-oxide films for MOSFET fabrication at low temperature. View full abstract»

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  • 50-Å gate-Oxide MOSFET's at 77 K

    Page(s): 2129 - 2135
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    While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin gate-oxide (52-Å) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-induced degradation may not be the limiting factor in choosing the power-supply voltage and special drain structures may be necessary for very thin gate MOSFET's even at 77 K. However, mobility reduction at high VGis more severe both at lower temperatures and for thinner oxides. Electron mobility appears to be oxide-thickness-dependent at 77 K. The dependence of the electron mobility on the normal field is so strong that it results in unusual I-V characteristics such as negative transconductance at 77 K for an oxide field above 3 MV/cm. The I--V characteristics have been modeled with a mobility dependence on VGSof the form µn ∞ (1 + η(VGS- Vt/Tox)2+ (E/Ec))-1for 52-Å devices. View full abstract»

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  • Design optimization of JCMOS structures

    Page(s): 2136 - 2145
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    JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure. View full abstract»

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  • Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

    Page(s): 2146 - 2152
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    This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively. View full abstract»

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  • Schottky base edge leakage in Si permeable-base transistors

    Page(s): 2153 - 2155
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    The base leakage/breakdown mechanism in the Si permeable-base transistor (SiPBT) is related to the radius of curvature of the depletion region directly below the edge of the metal semiconductor interface. The unique geometry of the SiPBT illustrates the edge breakdown phenomena. As higher reverse bias is applied to the base-collector junction, the adjacent depletion regions in the grating fuse and the exposed edge perimeter will vary to form a kink in the IV characteristics. The grating will self-guard. As the SiPBT design parameters are scaled to finer gratings, the carrier concentration under the base must increase to maintain permeable-base transistor action. These fine-period SiPBT's will also self-guard within the grating region. View full abstract»

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  • Latchup performance of retrograde and conventional n-well CMOS technologies

    Page(s): 2156 - 2164
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    The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+epitaxial material. View full abstract»

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  • Space-charge-limited currents in materials with nonlinear velocity-field relationships

    Page(s): 2165 - 2172
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    A general parametric form of the current-voltage characteristic of space-charge-limited currents (SCLC) is derived in the virtual cathode approximation. The result is used to obtain several new exact solutions for the trap-free insulator that is characterized by a nonlinear velocity-field (ν - F) relationship. Unlike previously reported results, the new solutions describe the gradual transition from the regime of constant mobility to that of the field-independent drift velocity. The first- and second-order corrections to the Mott-Gurney law then are obtained in a closed form for an important class of velocity-field relationships. Exact solutions are also Obtained for ν - F models that exhibit negative differential mobility behavior. The theory developed in this work is in good agreement with existing experimental data. The general result is used to specify the Condition that allows us to extract the anode field as well as the ν - F dependence from experimental current-voltage characteristics without assuming any a priori ν - F relation. In particular, such extraction is possible for the ideal trap-free insulator or materials with shallow traps. We illustrate the new approach by utilizing available experimental data to extract the ν - F dependence in GaAs. View full abstract»

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  • Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

    Page(s): 2173 - 2177
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    Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts. View full abstract»

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  • Origin of 1/f3/2noise in GaAs thin-film resistors and MESFET's

    Page(s): 2178 - 2184
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    This paper addresses the problem of 1/f3/2low-frequency noise in GaAs thin-film resistors and MESFET's. Experimental data seem to rule out the existence of the so-called "diffusion noise" usually invoked in GaAs devices. Therefore, we propose a new "surface thermal-noise" model based on the existence of lumped thermal-noise generators distributed along the semiconductor-air or semiconductor-dielectric protection interface. The observed dependence of the low-frequency noise on the surface resistance of different MESFET's supports our conclusions. View full abstract»

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  • Resonant tunneling device with multiple negative differential resistance: Digital and signal processing applications with reduced circuit complexity

    Page(s): 2185 - 2191
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    A new approach to obtain multiple peaks in the current-voltage characteristic of a resonant-tunneling (RT) device is demonstrated. The peaks are generated using only the ground state resonance of the quantum well rather than several states, as in conventional RT devices. The separation between the peaks is voltage tunable and also the peak currents can be made nearly equal, which is necessary to use the device in a variety of circuit applications. A functional device operating at 100 K, with two peaks in the I-V has been fabricated. The first practical demonstration of circuits for frequency multiplication by a factor of five, a three-state memory and a 4-bit parity generator, using a single functional RT device each, is also reported. The use of multiple-peak RT devices in these circuits results in an order of magnitude reduction in the number component per function over conventional techniques. View full abstract»

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  • High dI/dT light-triggered thyristors

    Page(s): 2192 - 2199
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    Directly light-triggered, 4000- and 6000-V thyristors were designed, fabricated, and tested to obtain high performance in dI/dt, dV/dt, and photosensitivity. Built-in resistors protected both auxiliary stages during high dI/dt turn-on. The novel use of etched moats to define the resistors was compatible with an optical gate structure that gives high dV/dt and good photosensitivity. No additional processing steps were needed to fabricate these devices, as compared to standard light-triggered thyristors. A record value of 1000 A/µs at 60 Hz was measured on a 6000-V thyristor, and 850 A/µs was safely triggered with only 1.8 mW of light. The dV/dt immunity of the photogate structure measured 4000 V/µs, rising exponentially to 80 percent of 4000 V, VDRM. Thyristors triggered by dV/dt were not destroyed. A new model of resistor heating was combined with the first measurements of the current pulses through both built-in resistors to identify the mechanism responsible for occasional burn-out of the second resistor. The failure mechanism was conductivity modulation in the surface of the resistor during its microsecond on-time caused by thermally generated carriers. The test results confirmed the utility of built-in resistors for high dI/dt performance with minimal light power and for nondestructive dV/dt triggering. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego