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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan. 1987

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  • [Front cover and table of contents]

    Publication Year: 1987 , Page(s): c1
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    Freely Available from IEEE
  • Foreword

    Publication Year: 1987 , Page(s): 1 - 3
    Cited by:  Papers (8)
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  • Technology for liquid-nitrogen-cooled computers

    Publication Year: 1987 , Page(s): 4 - 7
    Cited by:  Papers (12)
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    Computers requiring 1 to 400 W of refrigeration at 78 K can use standard commercial Gifford-McMahon-type refrigerators similar to those being produced for cryopumps. The computer elements would be immersed in a liquid-nitrogen bath in which heat transfer between the circuit elements and the bath can carry away 5 W/cm2. The elements would operate very near the 78-K bath temperature. Vapors from the boiling liquid would be recondensed on the cold refrigerator, located above the bath, and would fall back into the bath. For smaller computers, simple Joule-Thomson refrigerators could be developed. For larger refrigerators, reverse Brayton cycle refrigerators could be developed. View full abstract»

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  • Performance and hot-carrier effects of small CRYO-CMOS devices

    Publication Year: 1987 , Page(s): 8 - 18
    Cited by:  Papers (34)  |  Patents (3)
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    The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides. View full abstract»

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  • Submicrometer-channel CMOS for low-temperature operation

    Publication Year: 1987 , Page(s): 19 - 27
    Cited by:  Papers (67)  |  Patents (3)
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    A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K. View full abstract»

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  • A low-temperature NMOS technology with Cesium-implanted load devices

    Publication Year: 1987 , Page(s): 28 - 38
    Cited by:  Papers (12)  |  Patents (24)
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    A 2-µm enhancement/depletion-type NMOS technology designed for operation at liquid-nitrogen temperature is described. A cesium oxide implant has been used to realize load devices that are not degraded by the freeze out of mobile carriers that occurs in the bulk of conventional depletion-mode transistors at low temperature, Unloaded ring oscillators, fabricated using this technology, have an average propagation delay of 360 ps/stage and a power dissipation of 190 µW/stage with a 2.5-V power supply at 77 K; this represents an improvement in speed of a factor of 2.5 over a conventional NMOS technology operating at room temperature. Simulations predict a further decrease in delay to 200 ps/stage for a 2-/µm process may be achieved through optimization of the Cs-implanted load device without compromising noise margins. View full abstract»

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  • Low-temperature operation of silicon surface-channel charge-coupled devices

    Publication Year: 1987 , Page(s): 39 - 51
    Cited by:  Papers (2)
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    This paper presents results of the measurement and modeling of the temperature dependence of the charge-transfer inefficiency (CTI) on n- and p-channel surface-channel charge-coupled devices (CCD's) over the 25-300 K temperature range. The CTI was measured at clocking frequencies of 1, 10, and 40 kHz with minimum values of 0.00075 and 0.00018 reached near 50 K for the n- and p-channel devices, respectively. The CTI was modeled in terms of the interaction of the signal charge with an energy-dependent interface state density distribution. At temperatures above 200 K, thermally generated carriers or dark current modify the simple dependence on the interface state density distribution. The two-part model correctly simulates the dependence of the CTI on both the temperature and the frequency of operation. Fractional loss measurements were used to study surface state parameters. Other features of CCD low temperature operation measured and modeled include the input stage equilibration process. View full abstract»

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  • Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures

    Publication Year: 1987 , Page(s): 52 - 57
    Cited by:  Papers (4)  |  Patents (3)
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    The dependence of submicrometer-channel CMOS performance on surface orientation is measured for LDD devices at both 300 and 77 K. Special emphasis is placed on determining the optimum crystalline plane for CMOS operating at low temperatures (CRYO-CMOS). A comparison of transistor parameters is experimentally made between View full abstract»

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  • On the resistivity of TiSi2: The implication for low-temperature applications

    Publication Year: 1987 , Page(s): 58 - 63
    Cited by:  Papers (3)
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    The electrical resistivity of TiSi2formed on polysilicon implanted with phosphorus and arsenic and on n+and p+diffusions implanted with arsenic and boron was measured in the 4.2-300 K temperature range. It is found that in all cases, the resistivity is reduced by a factor of 3-4 when TiSi2is cooled from room to liquid-nitrogen temperature. Sheet resistance as low as 1 Ω/sq. at liquid-nitrogen temperature can be easily achieved for self-aligned thin TiSi2layers over polysilicon and diffusion regions, which is very attractive for low-temperature CMOS applications. The residual resistivity ratio, which is a measure of the electron mean free path, decreases with growing surface concentration of dopants, regardless of doping species. The analysis of thickness effects in terms of surface scattering and of grain boundary resistivity models, suggests that degradation of sheet resistance Rswith increased implantation dose is due only partly to the difficulty in forming thick enough TiSi2at high doses, and that dopant impurities segregated at the grain boundaries can account for the observed increase. View full abstract»

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  • Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology

    Publication Year: 1987 , Page(s): 64 - 74
    Cited by:  Papers (47)
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    This work characterizes the temperature, channel length, and voltage dependences of substrate current, and presents a local model describing this behavior using Shockley's lucky electron (LE) model as a basis. For n-channel (p-channel) devices, the model is extended using a Maxwell-Boltzmann (MB) distribution of hot-electron (hole) energies above (below) the conduction (valence) band minimum (maximum). The model has been implemented in CADDET, a 2-D device simulator, and is able to explain all of the important features of substrate current which have been reported to date. The model is discussed in the context of works which look at both the local and physical nature of the impact ionization phenomenon. Based on this discussion, the model's parameters are shown to have a solid physical basis, requiring no reliance on curve fitting. The agreement between data and simulations thus enhances physical understanding of substrate current in MOSFET's, and warrants confident design of CMOS technologies for cryogenic operation. View full abstract»

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  • Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

    Publication Year: 1987 , Page(s): 75 - 82
    Cited by:  Papers (23)
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    Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient. View full abstract»

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  • Analyzing hot-carrier effects on cold CMOS devices

    Publication Year: 1987 , Page(s): 83 - 88
    Cited by:  Papers (13)
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    The operation of discrete and integrated CMOS ring oscillators was evaluated over the temperature range 77-300 K. Gate delays typically decreased by a factor of two at 77 K. Hot-carrier effects were enhanced by low-temperature operation, and transistor transconductance degradation occurred at low temperatures, which did not occur at room temperature as measured in the forward and inverse transistor curves. In marked contrast to dc stressing, ac stressing caused very little circuit degradation at low temperatures. By modeling the low-temperature phenomena at the MOSFET source junction, both hot-electron and hot-hole carrier effects were analyzed. View full abstract»

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  • A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation

    Publication Year: 1987 , Page(s): 89 - 93
    Cited by:  Papers (62)
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    This paper reports on a semi-empirical model of the mobility in the inversion layer of enhancement-type MOSFET's operated at low temperatures. The n-channel model is based on three different scattering mechanisms important at cryogenic temperatures--phonon, Coulomb, and surface roughness scattering. It is shown that the degradation of the mobility with the vertical field is accelerated at low temperatures and has a different functional form compared to that at the above room temperature. The p-channel model is the extension of a high-temperature model. The simple analytical expression presented here is suitable for use in a circuit simulation program like SPICE. The definition and the temperature dependence of the effective normal field are reexamined for both n- and p-channel devices. View full abstract»

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  • Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

    Publication Year: 1987 , Page(s): 94 - 100
    Cited by:  Papers (7)  |  Patents (1)
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    Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 µm. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively. View full abstract»

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  • Switching characteristics of scaled CMOS circuits at 77 K

    Publication Year: 1987 , Page(s): 101 - 106
    Cited by:  Papers (15)
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    Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations. View full abstract»

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  • Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

    Publication Year: 1987 , Page(s): 107 - 113
    Cited by:  Papers (12)
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    Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed. View full abstract»

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  • MOSFET behavior and circuit considerations for analog applications at 77 K

    Publication Year: 1987 , Page(s): 114 - 123
    Cited by:  Papers (14)
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    We present an investigation into the behavior of silicon MOS transistors and analog circuits operated at liquid-nitrogen temperature (LNT). Simple scaling rules are used to predict the LNT performance of CMOS operational amplifier circuits designed for room-temperature operation. Measurements show that unity gain frequency and slew rate can be improved by the same amount as the mobility increase with no loss of stability if bias currents are properly controlled. We also show that room-temperature CMOS amplifier circuits can be redesigned for 77-K operation by reducing channel widths and compensation capacitor area, giving performance equal in most respects to that of unscaled circuits at room temperature. However, 1/f noise is degraded by such redesign. Similar considerations of NMOS amplifiers show that such circuits do not benefit greatly from operation at liquid-nitrogen temperature. To aid in studying the temperature dependence of the sheet resistance of diffused resistors, a computer program was developed based on available models for bulk mobility and carrier freeze-out. Accurate predictions require a temperature dependence for lattice scattering that differs from previously reported values. View full abstract»

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  • GaAs slow-wave phase shifter characteristics at cryogenic temperatures

    Publication Year: 1987 , Page(s): 124 - 129
    Cited by:  Papers (7)
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    It has been previously demonstrated that a single elemental solid-state GaAs epitaxial device, based on slow-wave electromagnetic propagation, can provide substantial variable phase shift in the microwave frequency regime at room temperature. Further, it has been shown that the insertion loss L of the device is reduced by increasing the conductivity in the transmission line metallization. Low-temperature applications make it desirable to determine if such a device can operate at cryogenic temperatures demonstrating useful phase-shifting properties. We have developed an accurate reliable cryogenic experimental test setup and procedure capable of measuring the phase shift θ and insertion loss L of a 1.6-mm-long device embedded in a waveguide system several meters long. Measurements have been made at 4.2, 77, and 309 K over a frequency range from 2 to 18 GHz. The 300-K results agree extremely well with earlier work and substantiate that very accurate measurements in such a setup are possible. The cryogenic results at 77 K produce a differential phase shift of 155° compared to 229° at 300 K. Loss reduction is most dramatic at frequencies below about 14 GHz and becomes progressively less as 18 GHz is approached. For example, at a Schottky bias voltage of 0.5 V, L is reduced by a factor of 2.3, 2.2, and 2.4 at 2, 10, and 12 GHz, respectively. Similar loss reduction factors are found up to 14 GHz for the 0.0-V bias case. Device operation at 4.2 K produces a differential phase shift of 206° and not much change in loss values compared to 77 K. View full abstract»

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  • Non-ideal base current in bipolar transistors at low temperatures

    Publication Year: 1987 , Page(s): 130 - 138
    Cited by:  Papers (38)
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    Bipolar transistors havetraditionally been considered not useful in low-temperature applications. This assumption, however, is based upon an incomplete physical understanding of bipolar device physics at low temperatures. This paper shows experimentally that recombination mechanisms play a substantially larger role in determining base current at low temperatures than at room temperature. The results are explained and quantitatively modeled using conventional Shockley-Read-Hall theory, with the addition of the Poole-Frenkel high field effect. It is concluded that trap levels in the silicon bandgap due to bulk traps or interface states are very important in determining bipolar transistor base currents at low temperatures. Non-ideality factors larger than 2 are often observed. Such trap levels will have to be carefully controlled if low-temperature operation of bipolar transistors is to be considered. View full abstract»

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  • The temperature dependence of the amplification factor of bipolar-junction transistors

    Publication Year: 1987 , Page(s): 139 - 142
    Cited by:  Papers (10)
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    It is widely known that the current gain of the bipolar transistor is degraded by low-temperature operation. However, the temperature dependence of another important parameter, the amplification factor, has not been reported. This brief presents theory and experimental results demonstrating the temperature independence of the Early voltage, and showing as a consequence that the amplification factor is inversely proportional to temperature. Using this information and the bandgap narrowing theory for current gain reduction, predictions and measurements are offered for simple bipolar amplifier circuits. Furthermore, the product of the current gain and amplification factor is proposed as a figure of merit for the transistor. The temperature that optimizes the gain product can be below 100 K for transistors with current gains that are weak functions of temperature. View full abstract»

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  • Temperature range extension and boundary condition modifications for the MOSCAP C-V simulation program

    Publication Year: 1987 , Page(s): 142 - 143
    Cited by:  Papers (4)
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    Modifications to the MOSCAP computer program extend the temperature range down to 7 K, and gate voltage is introduced as an input parameter instead of surface potential. The modifications do not affect computational efficiency or accuracy. View full abstract»

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  • [Back cover]

    Publication Year: 1987 , Page(s): c4
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    Freely Available from IEEE

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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