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Electron Device Letters, IEEE

Issue 6 • Date June 1986

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Displaying Results 1 - 23 of 23
  • [Front cover and table of contents]

    Publication Year: 1986 , Page(s): c1
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    Freely Available from IEEE
  • A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress

    Publication Year: 1986 , Page(s): 337 - 339
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A method to evaluate hot-carrier-induced NMOSFET degradation under dynamic stress is discussed, based on an empirical relation between device lifetime and substrate current in static stress. The device lifetime τ under dynamic stress is given by \tau = A.I_{sub,peak}^{-2.5}/R , where I_{sub,peak} is the peak value of pulsive substrate current and R is its duty ratio. The device lifetime experimentally obtained in an inverter circuit is in good agreement with the calculation results obtained from the proposed method. This method is useful to estimate device lifetime in actual circuit operational conditions. View full abstract»

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  • Analytical modeling of the subthreshold current in short-channel MOSFET's

    Publication Year: 1986 , Page(s): 340 - 343
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases. View full abstract»

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  • Analytical explanation to double-hump substrate current in funnel-shape transistors

    Publication Year: 1986 , Page(s): 344 - 346
    Cited by:  Papers (1)
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    Measurements of double-hump substrate current and enhanced gate current in funnel-shape (FS) MOSFET's have been recently reported [1]. In this letter an analytical explanation of these observations is given. It is shown that contrary to conventional transistors, the maximum lateral field along the channel of FS transistors operated in the wide-drain mode, and therefore the hot-carrier generation region, is shifted towards the source side as the gate voltage is increased. In addition, the maximum lateral field is increased at high gate voltages, giving rise to the abnormal increase of the substrate current. These results are derived from a simple one-dimensional solution of FS transistor characteristics. View full abstract»

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  • An electrical method to measure SOI film thicknesses

    Publication Year: 1986 , Page(s): 347 - 349
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    Others have identified three normal operating regions for silicon-on-insulator (SOI) MOSFET's. In two of these regions the threshold voltage depends on the silicon film thickness and the buried insulator thickness. Based on the threshold equations, a method has been developed to nondestructively measure the two film thicknesses. The method uses a feedback amplifier to hold the drain biases nearly constant while the body and/or the buried gate voltages are varied. Calculated threshold voltages from the top-gate voltages are used to calculate the film thicknesses. The method is illustrated on devices built in oxygen implanted substrates. Measurements compare well with SEM image measurements. View full abstract»

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  • Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

    Publication Year: 1986 , Page(s): 350 - 352
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10-14and 10-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10-14-10-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V. View full abstract»

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  • Ethanol sensitivity of palladium-gate metal-oxide-semiconductor structures

    Publication Year: 1986 , Page(s): 353 - 355
    Cited by:  Patents (1)
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    Hydrogen-sensitive palladium-gate MOS structures heated above 150°C show sensitivity to ethanol vapor. The effect is probably due to catalytic dehydrogenation of adsorbed ethanol molecules on the surface of the palladium gate. View full abstract»

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  • Slant-scanning and interstice-bridging methods used to produce highly uniform ZMR Si films on quartz wafers

    Publication Year: 1986 , Page(s): 356 - 358
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    Two methods are applied to zone-melting recrystallization (ZMR) using a graphite-strip heater to produce highly uniform and high-quality Si films on 3-in quartz wafers. The slant-scanning method was used to prepare grain boundary (GB)-free recrystallized Si films in 180- µm-wide stripes separated by 20 µm, and the interstice-bridging method was used to reduce the {111} texture generation to less than 1 percent. The average electron mobility and the average threshold voltage for MOSFET's were 960 cm2/V.s with a standard deviation of 43 cm2/V.s and 1.38 V with a standard deviation of 0.25 V, respectively. View full abstract»

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  • Reduction of extrinsic base resistance in GaAs/AlGaAs heterojunction bipolar transistors and correlation with high-frequency performance

    Publication Year: 1986 , Page(s): 359 - 362
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    Improved high-frequency performance in GaAs/AlGaAs heterojunction bipolar transistors (HBT's) by reduction of extrinsic base resistance is demonstrated. A new self-aligned process which is very simple, yet capable of producing 0.25-µm emitter-to-base contact gaps, is described. By the use of AuBe, we have also been able to produce contact resistances to p-type GaAs (p = 5 × 1018) as low as 1.2 × 10-7Ω.cm2. This is the lowest value reported to p-type GaAs considering the relatively low doping levels used. By employing these techniques, we have produced HBT's with 2.5-µm-wide emitters having current gain cutoff frequencies fTthat appear to be greater than 35 GHz and maximum oscillation frequencies f_{\max } of 22 GHz. View full abstract»

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  • Self-aligned-gate GaInAs microwave MISFET's

    Publication Year: 1986 , Page(s): 363 - 364
    Cited by:  Papers (11)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A self-aligned-gate GaInAs metal-insulator-semiconductor FET (MISFET) fabrication process that minimizes gate overlap capacitance and offers the potential of achieving submicrometer gate lengths is described. GaInAs MISFETs (1-µm gate length) fabricated with this process have given 0.49-W/mm gate width and corresponding power-added efficiencies of 48 and 39 percent at 4 and 8 GHz, respectively, at a drain voltage of 5.5. V. A small-signal gain of 3.2 dB was obtained at 15 GHz. The estimated carrier velocity was 1.7 × 107cm/s. More recent devices have carrier velocities of 2.5 × 107cm/s and are expected to have improved microwave performance. View full abstract»

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  • Determination of the Fowler-Nordheim tunneling barrier from nitride to oxide in oxide:nitride dual dielectric

    Publication Year: 1986 , Page(s): 365 - 367
    Cited by:  Papers (7)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    Using a simple but novel method of analysis, the voltage drop across the oxide (pad-oxide) in the oxide:nitride dual dielectric is determined for both positive and negative gate polarities. From the Fowler-Nordheim plot of the oxide voltage drop, the electron barrier from nitride to oxide is 3.2 ± 0.2 eV. However, the current injection from the nitride electrode is about 7 orders of magnitude lower than the current injection from the silicon electrode under the same oxide field values. This large field-current difference between the two directions of electron injection is consistent with the large difference observed in the J ★ t (charge fluence to breakdown) data. View full abstract»

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  • Oxidation-induced stress in a LOCOS structure

    Publication Year: 1986 , Page(s): 368 - 370
    Cited by:  Papers (12)
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    A two-dimensional oxidation model is introduced to analyze stresses induced in the oxide during silicon thermal oxidation for a local oxidation of silicon (LOCOS) structure. In this model, it is assumed that oxidation consists of two basic processes: oxidant diffusion into the oxide and viscoelastic deformation of the oxide. The equations describing these processes are solved using the boundary element method. Information on the stress distribution in the oxide suggests that the LOCOS oxide shape is closely related to the oxidation-induced stress. Consequently, this should prove useful in understanding thermal oxidation. View full abstract»

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  • Analysis of hot-carrier-induced aging from 1/f noise in short-channel MOSFET's

    Publication Year: 1986 , Page(s): 371 - 373
    Cited by:  Papers (18)
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    The 1/f noise of short-channel n-type MOSFET's is measured in the weak inversion regime before and after an electrical stress. The noise increase which follows the aging is shown to be due to an electrically induced generation of traps in the gate oxide rather than fast interface states. Noise experiments prove that the degradation occurs in a narrow region (less than 50 nm) near the drain. Created traps also appear to have an inhomogeneous energy profile. View full abstract»

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  • Evidence of long-term storage of minority carriers in N+-GaAs/AlGaAs/P-GaAs MIS capacitors

    Publication Year: 1986 , Page(s): 374 - 376
    Cited by:  Papers (3)  |  Patents (1)
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    We have investigated the long-term retention of electrons in potential wells at the AlGaAs/GaAs interface at 77 K. By analyzing the steady-state capacitance-voltage (CV) and current-voltage (I-V) characteristics of N+-GaAs/AlGaAs/P-GaAs MIS capacitors under illumination, we can calculate the leakage rate of electrons over the AlGaAs barrier as a function of the density of electrons in the well. At 77 K, we obtain storage times of 135 ms, and we estimate that the intrinsic storage time in the dark may be greater than 500 ms. These values would be suitable for the development of a one-transistor dynamic random access memory (RAM) in the MODFET technology. View full abstract»

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  • Preliminary ionizing radiation tests on n-channel inversion-mode GaInAs MISFET's

    Publication Year: 1986 , Page(s): 377 - 379
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    Preliminary results of low-dose rate ionizing radiation (cobalt-60) tests on n-channel inversion-mode GaInAs MISFET's up to a total dose of 5 × 107rad(Si) are presented. The data show that the GaInAs MISFET threshold voltage shifts negatively up to a total dose of 5 × 105rad(Si), with a maximum shift of -0.9 V. The threshold voltage then shifts in a positive direction at higher doses. The mobility factor decreases very slightly and then increases with increasing dose. View full abstract»

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  • Buried and graded/buried LDD structures for improved hot-electron reliability

    Publication Year: 1986 , Page(s): 380 - 382
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    New buried and graded/buried lightly doped drain (LDD) structures have been demonstrated, for the first time, to improve significantly the hot-electron reliability of NMOS devices. Both LDD structures have peak doping of the n- spacer implant approximately 1000 A below the Si-SiO2interface forming a "buried" n- spacer near the drain region. In the graded/buried LDD structure the junction of the "buried" n- spacer is further graded by an additional low-dose phosphorus spacer implant. View full abstract»

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  • Simple algebraic description of photoresist exposure and contrast enhancement

    Publication Year: 1986 , Page(s): 383 - 386
    Cited by:  Papers (1)  |  Patents (1)
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    Equations are given that allow the facile calculation of transmittance and concentration profiles for solid photosensitive systems of arbitrary optical absorbance, including absorbing photoproducts and medium. The results are applied to the measurement of resist exposure parameters, the determination of light intensity for a wafer stepper (dosimetry), and the analysis of contrast enhancement materials and other photobleaching image modification techniques. View full abstract»

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  • Fully implanted p-column InP field-effect transistor

    Publication Year: 1986 , Page(s): 387 - 389
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    P-column junction field-effect transistors (FET's) have been fabricated in semi-insulating InP utilizing an all-implanted planar technology. A periodic array of p+ columns implanted through an n-type channel layer is used to form the active region. Initial devices with nominal gate lengths of 4 µm exhibit a unity-power-gain frequency f_{\max } as high as 7 GHz while recent smaller gate length devices (nominally 1.7µm) show an f_{\max } of 16 GHz. View full abstract»

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  • Inversion-mode GaInAs MISFET ring oscillators

    Publication Year: 1986 , Page(s): 390 - 392
    Cited by:  Papers (11)
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    Inversion mode, self-aligned-gate, metal-insulator-semiconductor field-effect transistors (MISFET's) have been fabricated on p-type Ga0.47In0.53As epitaxially grown on semi-insulating InP substrates. Ring-oscillator (RO) circuits were designed using enhancement-driver/ enhancement-load-type logic gates. Propagation delay as low as 50 ps was measured in a nine-stage ring oscillator (driver MISFET about 1.2-µm gate length) with a fan-in and fan-out of one. These are believed to be the first results on GaInAs inversion-mode MISFET-based digital integrated circuits. View full abstract»

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  • An accurate dc model of 2-DEG FET for implementation on a circuit simulator

    Publication Year: 1986 , Page(s): 393 - 395
    Cited by:  Papers (6)
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    An accurate dc model for FET's using two-dimensional (2- D) carrier gas flow adjacent to the heterointerface is described. The model, based on novel empirical velocity-field curve, also takes into consideration a parallel conduction in a selectively doped layer. In addition, it depends primarily on physical rather than empirical parameters. The calculated results are in excellent agreement with experimental data, even for short-channel 2-D electron gas (2-DEG) FET's at 77 K. The present model will therefore be a promising candidate for implementation on a circuit simulator. View full abstract»

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  • Effects of a buried p-layer on alpha-particle immunity of MESFET's fabricated on semi-insulating GaAs substrates

    Publication Year: 1986 , Page(s): 396 - 397
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    Measurements of alpha-particle-induced charge are carried out for the first time on both conventional MESFET's fabricated directly on semi-insulating GaAs substrates and MESFET's with a buried p-layer. The maximum collected charge is found to be 65 fC in the MESFET's with a buried p-layer, one order smaller than in conventional MESFET's. View full abstract»

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  • Erratum

    Publication Year: 1986 , Page(s): 398
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  • [Back cover]

    Publication Year: 1986 , Page(s): c4
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    Freely Available from IEEE

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