By Topic

Electron Devices, IEEE Transactions on

Issue 4 • Date April 1986

Filter Results

Displaying Results 1 - 20 of 20
  • [Front cover and table of contents]

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (177 KB)  
    Freely Available from IEEE
  • n-p-n silicon lateral phototransistors for hybrid integrated optical circuits

    Page(s): 433 - 441
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    An etched mesa silicon lateral phototransistor (EMS-LPT) suitable for detecting the light signal from optical channel waveguides has been designed and fabricated. In this paper both n+-p-n+uniform base and n+-p-p--n+double-diffused EMS-LPT's are reported. The photoactive region of the EMS-LPT is highly localized and can be easily coupled either via an evanescent field or to a grating coupler on a channel waveguide. Light coupling, gain, speed, and signal-to-noise ratio of the device are thereby greatly improved. The fabrication techniques of the EMS-LPT's are compatible with those of MOSFET's, permitting integration of multiple EMS-LPT's and MOSFET load transistors to form optically addressed inverters on the same silicon chip. By flip-chip bonding LiNbO3and silicon substrates and coupling LiNbO3channel waveguides to EMS-LPT's via grating couplers, we produce electrooptic switches with optical input and output. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigation of MOS capacitors with thin ZrO2layers and various gate materials for advanced DRAM applications

    Page(s): 442 - 449
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    Thin ZrO2layers were used to realize MOS capacitors with aluminum, polysilicon, and molybdenum gate electrodes. The layers, 300-600 Å in thickness, were obtained by metal organic chemical vapor deposition. The effects of various high-temperature treatments as well as gate material deposition conditions on the MOS capacitor properties were studied. Processing conditions compatible with standard silicon technology were established to obtain capacitors suitable for advanced DRAM application. Relative dielectric constant ∈ ≥ 16, breakdown fieldE_{B} ge 3MV/cm, and leakage currents at applied voltage of 5V around 10-8A/cm2enable the realization of capacitors with dielectric layer equivalent to 35 Å of SiO2. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A twin-well CMOS process employing high-energy ion implantation

    Page(s): 450 - 457
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    A twin-well CMOS process has been developed using ion implantation with energies up to 1 MeV. The high-energy ion-implantation steps eliminate the need for extended processing times at high temperatures. As a consequence, this permits an increase in packing density, independent control of critical electrical parameters, and simplified processing. The resulting process includes advantages of recent developments in bulk CMOS: an n-type isolation well in a p-p+substrate and retrograde wells. This paper discusses the processing steps involved and provides the resulting device characteristics. An interesting application of the process is also presented, which is the realization of a gate array with TTL-compatible input and output buffers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A shallow flat p-well structure for interline-transfer CCD image sensors

    Page(s): 458 - 463
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    This paper describes a newly-developed image-sensing element having a shallow flat p-well (SFPW) structure, and further mentions its application to a 490 × 510- and a 580 × 500-element device for use in the ⅔-in optical format. The structure consists of a shallow flat p-well in the imaging area that incorporates not only photodiodes for blooming suppression but also CCD shift registers for reduction of smearing. Desirable features such as 1) high resolution, 2) high aperture ratio, and 3) low smearing level were facilitated simultaneously by a combination of the SFPW structure with a transfer gate-less (TGL) and clock-line-isolated photodiode (CLIP) structure. Here, the conventional n+-p photodiode is replaced by an n+-n--p structure, in which the n-region serves as an overflow duct to the substrate for excess charge generated by optical overloads. It also contributes to maintaining the sensitivity at medium wavelengths. Either of these two image sensors have horizontal resolution in excess of 370 TV lines, an aperture ratio of over 32 percent, and a smearing level of less than -70 dB. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A nitride-isolated molybdenum-polysilicon gate electrode for MOS VLSI circuits

    Page(s): 464 - 468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    A new gate electrode structure is demonstrated. The low-resistive gate electrode consists of a triple layer of molybdenum and polysilicon films isolated with an ultrathin silicon-nitride film, namely MTP-metal/tunneling nitride/polysilicon. The tunneling nitride, which is grown by direct thermal nitridation of silicon, avoids silicidation of molybdenum and diffusion of impurities resulting in a thin SiO2film of good quality. Characteristics of discrete FET's can be designed like those of conventional silicon-gate devices. No instability due to the tun, neling nitride has been observed in both dc and high-speed switching operations. The technique is useful for MOS VLSI circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computer modeling and comparison of different rectifier (M-S, M-S-M, p-n-n+) diodes

    Page(s): 469 - 476
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    A computer method is used to investigate the forward characteristics of high-barrier Schottky diodes with different back contacts. A discussion of rectifier-parameter optimization is presented, together with comparisons of different diode types, including p-n-n+diodes. The superiority, in certain voltage ranges, of the high-barrier Schottky diodes over p-n-n+diodes is demonstrated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Polycrystalline-silicon device technology for large-area electronics

    Page(s): 477 - 481
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    The process sequence used to fabricate post-hydrogenated polycrystalline silicon thin-film devices has a dramatic impact on performance. A near-optimal process for devices that have hole mobilities of up to 50 cm2/V . s and electron mobilities of 70 cm2/V . s is demonstrated. These observed mobilities are substantially higher than previous literature reports. Implantation of boron or phosphorus into the polycrystalline-silicon device channel after the gate-oxidation step allows threshold-voltage tailoring for achievement of either enhancement-or depletion-mode operation of n- and p-channel devices. These results indicate that CMOS or NMOS logic could be fabricated using polycrystalline-silicon devices. Devices with steam-grown gate oxides have reduced channel mobility in comparison with devices oxidized in dry O2at the same temperature. Possible mechanisms for the variation in performance with oxidation conditions are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sensitivity of dynamic MOS flip-flop sense amplifiers

    Page(s): 482 - 488
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    An approximate analytic expression for the sensitivity of a dynamic flip-flop sense amplifier is derived. The calculation includes the imbalance of the flip-flop, and the approximate solution is given by means of Lynch and Boll's method. The sensitivity, which is defined by the minimum difference in input voltages, consists of two terms; one is the center voltage deviation, which is characterized by the imbalance of the device parameters, and the other is the insensitivity-width term, which greatly depends on the choice of circuit parameters. In normal highly sensitive sense amplifiers used in dynamic memories, the insensitivity-width term can be sufficiently small and the sensitivity is dominated by the imbalance of device parameters such as threshold voltages, conductances, and capacitances. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new analytical three-dimensional model for substrate resistance in CMOS latchup structures

    Page(s): 489 - 493
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A new analytical model based on solving the three-dimensional Laplace equation has been developed to calculate the substrate-spreading resistance of a latchup-sensitive path in internal CMOS structures. This model also provides an analytical closed-form expression for the substrate potential as functions of the structural parameters in the substrate, the dimensions of majority-carrier injector, and the majority-carrier current density across the injector. The calculated results based on the developed model have been compared with existing experimental results, and good agreement has been obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

    Page(s): 494 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm2/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm2/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Resonant-microbridge vapor sensor

    Page(s): 499 - 506
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1088 KB)  

    A novel integrated vapor sensor is described that incorporates a polycrystalline silicon microbridge coated with a thin polymer film. The microbridge is resonated electrostatically and its vibration is detected capacitively using an integrated NMOS circuit. Vapor uptake by the polymer increases the mass-loading on the microbridge, thereby perturbing the first resonant frequency of the microbridge. In the prototype device, a 150-nm-thick layer of negative photoresist coats a 153-µm-long 1.35-µm-thick polycrystalline silicon microbridge. The phase between the excitation and output voltages at resonance is monitored as the sensor output signal. Exposure to saturated xylene vapor produces a phase shift of -8° with a response time of less than 7 min. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-loss high-speed switching device: The 2500-V 300-A static induction thyristor

    Page(s): 507 - 515
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1280 KB)  

    An anode-emitter shorted-type 2500-V 300-A buried-gate static induction (SI) thyristor was fabricated and resulted in a very-high-speed turn-on time of 2.0 µs and a turn-off time of 3.1 µs, both at 1000 A, and in very low-loss performance due to the reduction of the tailing current. The switching loss and the conduction loss of the high-power SI thyristor is for the first time evaluated in this paper. Snubber-circuitless operation is demonstrated for the first time for the high-power SI thyristor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-frequency pseudogeneration—Recombination noise of MOSFET's stressed by channel hot electrons in weak inversion

    Page(s): 516 - 519
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    Up to now, the effect of trap distribution over distance in the oxide on low-frequency noise has not been verified experimentally. In this paper, a new method to detect the pseudo-g-r noise, caused by a nonuniform trap distribution, is proposed using MOSFET's stressed by channel hot electrons. The experimental results are interpreted well by the early given theories and show that the pseudo-g-r noise can be obtained provided that the MOSFET's are aged sufficiently by electrical stress and operate in weak inversion. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed CdS0.2Se0.8photoconductor and its application to line-image sensors

    Page(s): 520 - 525
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    The photoelectric properties of CdS1-xSex(x = 0.4-1.0) photoconductor-type sensors were measured. The sensors were made by heat-treating an evaporated film under the influence of CdCl2vapor. The photocurrent Jpis large, and the dark current Jdis small; theS/Nratio derived from theJ_{p}/J_{d}ratio reaches a value of more than 60 dB. With increasingx, the decay time of the photocurrent decreases, while the rise time increases. By addition of continuous light bias, the rise time is drastically reduced. Furthermore, the decay time is reduced by increasing the applied voltage. These effects are pronounced for a CdS0.2Se0.8sensor. Using this sensor, we constructed a contact-type line-image sensor (8 bits/mm, 1728 bits), and attained a scanning rate of 1 ms/line and a total time of about 2 s for reading an ISO A4 size document. The reading was performed under an application of 20 V, and an illumination of 7.5-µW/cm2light bias and 15 µW/cm2(∼100 lux) signal light using LED light sources (570 nm). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 30-ps Si bipolar IC using super self-aligned process technology

    Page(s): 526 - 531
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comments on "A theory of the Hooge parameters of solid-state devices"

    Page(s): 532 - 533
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (303 KB)  

    Handel's "quantum theory of1/fnoise" (Q.T.) was developed in the above paper in an ambitious attempt to explain the ubiquity of1/fnoise [1]-[3]. The theory has been used to derive the Hooge equation [4], which in turn has been used for many years now in analyses of experimental data (e.g., [5], [6]). The purpose of this comment is to point out serious flaws in Q.T. and to list recent empirical results which are not explained by the Hooge formula or any of its revisions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reply to "Comments on 'a theory of the Hooge parameters of solid state devices'"

    Page(s): 533
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    We clarify here our use of the Hooge parameter and indicate what we mean with verifying Handel's quantum theory of the1/fnoise. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rebuttal to "Comments on 'a theory of the Hooge parameters of solid-state devices'"

    Page(s): 534 - 536
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    The basic ideas of the quantum1/fnoise theory are presented here briefly only up to the point needed in order to answer the questions raised by Dr. Black [1], and to clarify whether or not they contain new contributions or if they are just caused by lack of familiarity with the theory. All claims of inconsistencies and flaws in the theoretical framework are rejected as unfounded. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back cover]

    Page(s): c4
    Save to Project icon | Request Permissions | PDF file iconPDF (593 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology