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Electron Devices, IEEE Transactions on

Issue 6 • Date June 1985

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Displaying Results 1 - 25 of 25
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Quasi-Fermi level bending in MODFET's and its effect on FET transfer characteristics

    Page(s): 1017 - 1023
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    Using Shockley's diffusion/drift model we calculate the quasi-Fermi level (imref) bending in the depleted AIGaAs barrier layer of GaAs/AIGaAs MODFET's. We show that the assumption of a constant imref from the heterointerface through the barrier layer is not justified when the gate is moderately forward biased. Once the barrier-layer conduction band edge at the gate interface fails below that at the heterointerface, the imref changes both in the vicinity of the heterointerface and at the gate metal. This has important consequences for the MODFET transfer characteristics and necessitates new considerations for the gate control mechanism As a result, sheet electron concentrations in the MODFET channel exceeding the equilibrium concentrations are obtained. Despite the gate being forward biased with voltages close to or larger than the Schottky-barrier height, the gate current is suppressed not only by the barrier at the heterointerface but also by a barrier of about the same height present at the gate metal-semiconductor interface. Experimental results on AIGaAs/GaAs MODFET's are in good quantitative agreement with the theoretical calculations. View full abstract»

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  • An analysis of the thermal response of power chip packages

    Page(s): 1024 - 1033
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    Since power densities in integrated circuits and power semiconductor devices are continuously increasing due to miniaturization of circuitry, the design of optimum heat spreaders and heat sinks for these applications requires rather sophisticated calculational methods. The chips and spreaders are usually rectangular in shape and although the problem is three-dimensional in nature, it is usually approximated by two-dimensional configurations. Steady-state and transient analytic solutions are presented for the axisymmetric, two-dimensional, and three-dimensional spreader geometries, which can be used to calculate the thermal resistance of the base alone. To determine the thermal resistance of the chip-base combination, the one-dimensional chip thermal resistance should be added to that of the base. These analytic solutions provide calculational means which are easier than the numerical methods. The exact analytic steady-state and transient solutions developed for the axisymmetric, two-dimensional, and three-dimensional configurations are in excellent agreement with the numerical calculations. The parametric calculations provide information on the important guidelines that a packaging engineer should bear in mind while designing and optimizing heat spreaders for power semiconductor applications. These points can be summarized as follows: 1) for a given chip area there exists an optimal base area, 2) increasing the base thickness initially decreases the thermal resistance and beyond a certain limit the latter increases with base thickness, and 3) the convective heat transfer coefficient strongly affects the thermal resistance and the usual assumption of an isothermal base is not always appropriate. View full abstract»

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  • The DSI diode—A fast large-area optoelectronic detector

    Page(s): 1034 - 1036
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    Fast double-Schottky-interdigitated diodes have been fabricated by evaporating Al-Schottky contacts on lowly doped n-GaAs (n=1014cm-3), These detectors have a relatively large light-sensitive area of 400 µm2. Rise and fall times are in the order of 10 ps. The external quantum efficiency is 25 percent at λ = 820 nm. The frequency response of the diodes is essentially flat up to 18 GHz, which is the limit of the measuring equipment. View full abstract»

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  • GaAs MESFET ring oscillator on Si substrate

    Page(s): 1037 - 1041
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    GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET with a 0.5 µm × 10 µm gate. The minimum delay time was 66.5 ps/ gate at a power consumption of 2.3 mW/gate. View full abstract»

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  • Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

    Page(s): 1042 - 1046
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    A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography. View full abstract»

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  • Noise associated with substrate current in fine-line NMOS field-effect transistors

    Page(s): 1047 - 1052
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    The noise manifested by impact-ionization-generated substrate current in fine-line NMOS transistors is studied. It is found that this noise can be considerably above the shot noise level for high drain voltages. The magnitude of this noise is interpreted in terms of an avalanche gain produced by a multistep impact-ionization process involving both holes and electrons. The device structure imposes one positive and one negative feedback loop and exhibits a peak in the noise as a function of the drain voltage. View full abstract»

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  • A multiplexer employing Josephson functional gates

    Page(s): 1053 - 1056
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    A new Josephson multiplexer is designed and analyzed. Experimentally, the multiplexer is fabricated by standard Pb alloy technology with 5-µm line width, and its operation is successfully performed. The typical operating margin is ±16 percent for the gate current. The multiplexer is a four-way multiplexer with a 2-4 decoder consisting of functional AND gates. The functional gates are composed of two asymmetric logics arranged in a series on its gate current line. These gates realize 2-4 decoder and data selector functions. The multiplexer offers advantages of integrated-circuit area reduction, low power dissipation, and high-speed operation. View full abstract»

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  • A novel impact-ionization model for 1-µm-MOSFET simulation

    Page(s): 1057 - 1063
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    In this work, a new formula for the impact-ionization process in silicon is derived. Compared with former descriptions, e.g., Chynoweth's law, this model offers the advantage to accurately calculate the ionization rates even in the case of nonhomogeneous electric fields. The idea of this model takes advantage of Shockley's "lucky-electron" model and the resulting formula is suited for implementation into device simulators to calculate impact-ionization-induced mechanisms. As an example, the model has been used together with the MINIMOS program to calculate the breakdown-voltage improvement of LDD MOSFET's. View full abstract»

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  • Doping effects and compositional grading in AlxGa1-xAs/GaAs heterojunction bipolar transistors

    Page(s): 1064 - 1069
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    First-order analytical calculations were made for the energy-band diagrams for n-AlxGa1-xAs/p-GaAs heterojunctions for x = 0.15, 0.3, and 0.5 employing different compositional gradings and doping densities specifically for heterojunction-bipolar-transistor (HBT)applications. In the calculations most recently determined, conduction-band discontinuity ΔECof 65 percent of the bandgap difference ΔEgbetween the AlxGa1-xAs and GaAs, and the donor activation energies in n-AlxGa1-xAs of 60 and 160 meV for x = 0.3 and 0.5, respectively, were used. The results show that the position of the heterojunction spike barrier, and the depth and width of the notch in the conduction-band edge for a compositionally abrupt heterointerface depend on the respective doping densities on the p and n sides of the heterojunction. Also, for an abrupt heterointerface the difference in barrier heights for electron and hole injections varies between ΔEgand ΔEV(the valence-band discontinuity), depending on the doping densities and the applied bias, and is not necessarily the generally accepted value of ΔEV. Analytical expressions and curves were obtained to estimate the minimum compositional grading L for eliminating the spike barrier and the notch as a function of the doping densities and the applied bias. View full abstract»

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  • Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities

    Page(s): 1070 - 1076
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    Gummel's integral charge-control relation (ICCR) IC= (const/Qp).exp (VBE/VT) is an important basis for developing self-consistent compact transistor models for the high-current region (including quasi-saturation). Such models are required for the simulation of future high-speed IC's with a high integration level. Unfortunately, the simplifying assumptions on which the ICCR is based seem to be doubtful especially for very fast transistors. Therefore, in this paper, the ICCR and its assumptions are checked via numerical simulation of such transistors (fT≈ 7-8 GHz). It is found that the one-dimensional ICCR is a fairly good approximation far into the high-current region. This satisfactory result is mainly due to the partial compensation of the influences of the spatially dependent doping concentration on both the electron mobility µnand the effective intrinsic density niewithin the product µnn2ie. Only in the emitter and in the emitter-base space-charge region there is a strong increase of this product which, in conjunction with the increasing contribution of the hole charge in these regions, was proved to be responsible for the errors observed at high current levels. The ICCR can also be applied to a two-dimensional transistor by additionally taking into account the excess hole charge stored outside the internal transistor for the determination of Qp. Thus the contribution of the minority charges can still be determined experimentally by measuring τf(IC). View full abstract»

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  • Bidirection shift plasma display requiring less than 20 drivers

    Page(s): 1077 - 1081
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    A bidirection shift technique has been successfully demonstrated on a 512 × 120 cell array of a standard ac plasma panel. The key features of the bidirection shift technique are: electron transport for efficient information transfer, preset wall voltage for select-shift and timed select-erasure for automatic error clearing. The technique reduces the number Of line drivers to 2 four-phase drivers and 7 line drivers. A shifting speed up to 800 characters/s has been achieved with good operating voltage margins. View full abstract»

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  • A receiver circuit for Josephson computer chip-to-chip logic signal transmissions

    Page(s): 1082 - 1085
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    A receiver circuit for the transmission of logic signals through package connectors in a Josephson computer is developed. It utilizes new circuit construction. This construction gives operation unaffected by the noise which is induced on the signal transmission paths by high-frequency and high-level ac power current at the connectors. The power current noise reduction ratio at a power frequency of f = 250 MHz, which corresponds to a 2-ns machine cycle, is experimentally confirmed to be 0.15. View full abstract»

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  • Ring oscillator circuit simulation with physical model for GaAs/GaAlAs heterojunction bipolar transistors

    Page(s): 1086 - 1091
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    Switching performance is simulated for GaAs/GaAlAs heterojunction bipolar transistors (HBT's) by combining a realistic physical device model that involves numerical solutions for carrier transport equations and Poisson's equation with our own circuit simulator that enables direct access to the device model embedded in arbitrary circuits. Based on simulated results for five-stage ring oscillators, discussion is given as to how the switching performance depends on the circuit configuration such as current mode logic (CML) without and with emitter follower, and direct-coupled transistor logic (DCTL), inclusion or exclusion of external base areas, and choice for single-or double-heterojunction transistors. View full abstract»

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  • Two-dimensional transient simulation of an idealized high electron mobility transistor

    Page(s): 1092 - 1102
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    We develop a model for the high electron mobility transistor (HEMT) in which we include both hot-electron effects and conduction outside the quantum subband system using hydrodynamic-like transport equations. With such a model we can assess the significance of the various physical phenomena involved in the operation of the HEMT. We calculate results with a two-dimensional numerical technique for both steady-state and transient operation. For a 3-µm device at 77 K, we determine a transconductance of 450 mS/mm, a current-switching speed of 6 ps, and a capacitive charging speed of 4 ps/fanout gate which corresponds to the performance measured by other workers. We also see that electronic heating, velocity overshoot, and conduction outside the quantum well are significant near the pinchoff point. We conclude that the advantage of HEMT is twofold. The excellent conduction in the quantum well results in a low access resistance, and the low impurity concentration in the GaAs results in optimum overshoot effects. View full abstract»

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  • A unified circuit model for bipolar transistors including quasi-saturation effects

    Page(s): 1103 - 1113
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    This paper describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both de and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor. In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement. View full abstract»

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  • A source coupled FET logic—A new current-mode approach to GaAs logics

    Page(s): 1114 - 1118
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    This paper describes the basic properties of the source coupled FET logic (SCFL) in terms of the dc characteristics, the speed and power performance, and other inherent features. Simulation results are compared to those for the direct coupled FET logic (DCFL), demonstrating that the SCFL has a wide allowable threshold voltage range, an excellent fan-out capability, a small input capacitance, a high input sensitivity, and a versatility for the application. View full abstract»

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  • Contacts on GalnAs

    Page(s): 1119 - 1123
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    The specific contact resistance ρcof Ni/Au-Ge/Ni and Ni/Au-Sn/Ni layers on n-GaInAs and Ni/Au-Mg/Ni and Ni/Au-Zu/Ni on p-GaInAs are measured for different alloying temperatures and times using an extended transmission line model. Specific contact resistances of 4.10-8Ω cm2for Ni/Au-Sn/Ni on n-GaInAs (n = 1018cm-3) and 2.10-5Ω. cm2for Ni/Au-Zn/Ni on p-GaInAs (p = 1018cm-3) are obtained. After deposition at room temperature, the barrier height of the metal-n-GaInAs system was determined to be 0.16 eV, decreasing below 20 meV after heat treatment. Interdiffusion of metal and semiconductor was investigated by SIMS/Auger measurements. At alloying temperature of 300°C the contacts show fast diffusion of Au relative to the dopants, effecting an increase of the specific contact resistance. View full abstract»

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  • Quartz versus PBN—The effect of crucible type on undoped LEC GaAS

    Page(s): 1124 - 1129
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    Undoped semi-insulating GaAs crystals were grown in a low pressure LEC system using quartz and pyrolytic boron nitride (PBN) crucibles. Crystals grown in PBN crucibles are consistently semi-insulating from the seed end to the tail end. Crystals grown in quartz crucibles have lower Hall mobility. Other properties such as dislocation etch-pit of conductive material beginning from the seed end of the crystal, and have lower Hall mobility. Other properties such as dislocation etch-put density, implant profile, and thermal conversion characteristics of the two types of crystal are about the same. View full abstract»

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  • Gallium arsenide Schottky power rectifiers

    Page(s): 1130 - 1134
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    This paper discusses the development of high-performance gallium arsenide Schottky rectifiers for power switching applications. These diodes are shown to exhibit superior turn-on and turn-off dynamic switching characteristics when compared with silicon p-i-n rectifiers. The theoretical analysis presented in the paper indicates that the gallium arsenide Schottky power rectifier will be attractive for high-frequency power switching circuits operating at 1.00-300 V. View full abstract»

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  • A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

    Page(s): 1135 - 1139
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    A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n+implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltage \partial V_{th} , and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained. View full abstract»

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  • Fabrication of fully self-aligned joint-gate CMOS structures

    Page(s): 1140 - 1142
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    A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and PMOS transistors have been characterized and together are functional in joint-gate CMOS inverters. View full abstract»

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  • A formula for the concentration profile of a buried layer with back diffusion

    Page(s): 1142 - 1143
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    A simple formula allows an accurate dopant concentration profile to be calculated for a Gaussian buried layer with back diffusion into an epitaxial layer. The formula is valid when the drive-in diffusion is dominant, when the back diffusion is dominant, and for intermediate cases. View full abstract»

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  • Improved convergence of numerical device simulation iterative algorithms

    Page(s): 1143 - 1145
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    Two techniques are described which serve to minimize the problem of slow Newton convergence and, at times, divergence sometimes experienced in applying this iterative technique to the solution of nonlinear semiconductor equations. The truncated correction method limits the wide excursions in the solution parameters which can occur during the Newton iterative procedure and thereby permits fewer voltage increments to be used in applying large bias voltages (1000 V)in simulating semiconductor power device operation. The doping-incrementation method uses the technique of gradually incrementing the doping levels in the heavily doped regions in a device structure to provide better solution first guesses in the simulation of devices containing such regions. Substantial savings in computer time are obtained in applying these two numerical procedures. View full abstract»

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  • [Back cover]

    Page(s): c4
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    Freely Available from IEEE

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

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University of California San Diego