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Electron Devices, IEEE Transactions on

Issue 3 • Date March 1985

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Displaying Results 1 - 25 of 37
  • [Front cover and table of contents]

    Publication Year: 1985 , Page(s): c1
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    Freely Available from IEEE
  • On-line extraction of model parameters of a long buried-channel MOSFET

    Publication Year: 1985 , Page(s): 545 - 550
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    A buried-channel depletion MOS transistor has an implanted neutral conducting channel between the source and drain due to which the device works in a variety of modes such as accumulation, accumulation-depletion, depletion, inversion-depletion, inversion, etc., and presents a more complex structure than an enhancement-mode device. For precise circuit simulation, accurate and on-line extraction of model parameters has assumed significant importance. It is found that representing the implanted buried channel by an equivalent box with average doping and junction depth gives a convenient trade-off between simplicity in modeling and accuracy in device characterization. The present work proposes a method of deriving the necessary model parameters through the measurement of a single device parameter, namely drain conductance under different operating conditions. The on-line measurements carried on a boron-implanted relatively long buried-channel MOSFET have been used to predict the best box for the profile and give other model parameters necessary for circuit simulation. It is shown that the method is most insensitive to measurement conditions compared to other techniques. View full abstract»

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  • Dependence of photoinduced changes in photovoltaic and dark electrical properties of hydrogenated amorphous silicon diodes on changes in the film properties of hydrogenated amorphous silicon

    Publication Year: 1985 , Page(s): 551 - 558
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    Computer simulation of hydrogenated amorphous silicon (a-Si:H) p-i-n type or n-i-p type diodes has been used to clarify the relationship between the photoinduced changes in photovoltaic and dark electrical properties of a-Si:H diodes and those in a-Si:H film properties. The origins of observed decrease in the short-circuit current and the fill factor are discussed referring to the decrease in carrier lifetimes, the change in electric field distribution in the undoped layer reflecting the increase in the density of ionized gap states, and the increase in interface recombination velcoity. Possible reasons for the observed differences in the photoinduced changes in photovoltaic properties between p-i-n type and n-i-p type a-Si:H diodes are also discussed. The observed changes in dark current-voltage characteristics of a-Si:H diodes can originate from the decrease in carrier lifetime. Some comments are also made on the "bulk or surface problem" of the photo-induced changes in a-Si:H p-i-n or n-i-p diodes. View full abstract»

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  • Mobility degradation in very thin Oxide p-channel MOSFET's

    Publication Year: 1985 , Page(s): 559 - 561
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    The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results. View full abstract»

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  • Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

    Publication Year: 1985 , Page(s): 562 - 570
    Cited by:  Papers (13)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions. View full abstract»

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  • Correlation between the backgating effect of a GaAs MESFET and the compensation mechanism of a semi-insulating substrate

    Publication Year: 1985 , Page(s): 571 - 576
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The backgating effect on FET'S fabricated both on a Cr-doped HB and on an undoped LEC substrate is investigated. The deep impurity compensation is found to influence the backgating effect both through the formation of the electric dipole layer at the interface between the n-channel and i-substrate, and through the voltage drop in the semi-insulating substrate. View full abstract»

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  • Characterization of thermally oxidized n+polycrystalline silicon

    Publication Year: 1985 , Page(s): 577 - 583
    Cited by:  Papers (6)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    The properties of thermally grown silicon dioxide films on n+polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms. All of the above electrical parameters are found to be degraded by any increase in the degree of surface roughness at the oxide-polysilicon interface. Our results suggest that a significant improvement in the insulating properties of the SiO2films can be achieved if the polysilicon is initially deposited in the amorphous phase at 560°C rather than the polycrystalline phase at 620°C. For example, for dry-oxidized diffusion-doped films, there is an increase in oxide breakdown field from 3.0 MV . cm-1to 6.2 MV . cm-1, and a reduction in leakage (Fowler-Nordheim) current of two orders of magnitude. Furthermore, it is shown that the long-term reliability of n+polysilicon/SiO2/n+polysilicon structures is directly related to the degree of interface texture; i.e., a smoother interface will result in a significant reduction in electrical wearout and an increase in time to failure. View full abstract»

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  • Design tradeoffs between surface and buried-channel FET's

    Publication Year: 1985 , Page(s): 584 - 588
    Cited by:  Papers (118)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance. View full abstract»

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  • Novel split-gate MOSFET

    Publication Year: 1985 , Page(s): 589 - 593
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    A new type of split-gate MOSFET (SG-MOSFET) is described that employs a complementary poly-Si-gate buried-channel MOS process. In this configuration, complementary SG-MOS's provide higher transconductance and a one-order smaller magnitude of channel-length modulation than with conventional buried-channel MOSFET's. Moreover, there is no requirement for additional mask steps. Four-times higher packing density was also obtained in a differential amplifier application. View full abstract»

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  • Latchup criteria in insulated gate p-n-p-n structures

    Publication Year: 1985 , Page(s): 594 - 598
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    Latchup in insulated-gate p-n-p-n structures may be due either to the well-known thyristor action or to a regenerative feedback originating from substrate bias in the MOS gate. Simple models are presented to interpret and to predict both latching modes. It is shown that these two latching modes may occur consecutively as the current level rises, and that the device may, therefore, exhibit three distinct regions of forward operation. Experiments on special test devices in which the p-base region can be accessed externally support the theory well. View full abstract»

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  • Ionization rates of electrons and holes in GaAs considering electron-electron and hole-hole interactions

    Publication Year: 1985 , Page(s): 599 - 604
    Cited by:  Papers (1)
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    Calculations have been carried out for the ionization rates of electrons and holes in GaAs considering electron-electron and hole-hole interactions in addition to the optical phonon scattering, and the results have been compared with those of the experimentally observed values of both Ito et al. [1] and Pearsall et al. [2]. Fairly good agreement is found between the theoretical and experimental results. At the lower field region, the hole-ionization rate is larger than the electronionization rate and they meet at a field of the order of 108V/m depending on the carrier concentration and other parameters; then, the hole-ionization rate becomes less than the electron-ionization rate. For the hole-ionization rate, at lower field range, holes behave as spin-orbit splitoff holes while at higher field they behave as heavy holes. The present study confirms that carrier-carrier interaction plays an important role in explaining the experimental results of ionization rates of carriers in GaAs and may be true for other semiconductors also. View full abstract»

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  • Schottky-barriers on p-type GaInAs

    Publication Year: 1985 , Page(s): 605 - 609
    Cited by:  Papers (2)
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    On p-type Ga0.47In0.53As LPE-grown layers, Schottky diodes were fabricated with different metals and surface preparations. On chemically etched surfaces, diodes with ideality factors near unity but rather low breakdown voltages with soft breakdown were achieved. The barrier heights were between 0.4 and 0.7 eV depending on the work function of the metal. On sputter-cleaned surfaces the diodes exhibited high breakdown voltages and barrier heights of about 0.7 eV independent of the metal. Annealing of the diodes at 320°C resulted in reduced series resistances and barrier heights in the case of sputteretched surfaces. The junction seems to consist of two different barriers; the lower one is determined by an As segregation at the interface, whereas the higher one is caused by traps which are induced by the sputter process. View full abstract»

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  • Current polarity switching decoders for Josephson memory arrays

    Publication Year: 1985 , Page(s): 610 - 616
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB)  

    Two new types of Josephson decoder circuits have been devised, designed, fabricated, and tested. The circuits utilize current polarities along address loops as information. This results in simple circuit configurations with about half the number of circuit gates than conventional Josephson decoder circuits. This contributes to improved yield rates and to a decrease in circuit area. One of the two decoder circuitsz described in this paper can be operated with either dc or unipole while the other is unipole only. Using computer simulation, the operating speed for the former 5-32 decoder circuit is about 320 ps which is almost the same as that of conventional decoders, while for the latter circuit it is 115 ps which is almost half of that for the conventional decoders. The decoders are designed with operating margins of over ±35 percent which is sufficient for Josephson circuits. Critical path subsections of these two 5-32 decoder circuits were fabricated by standard lead-alloy technology and quasi-staticaUy operated successfully. View full abstract»

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  • Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon

    Publication Year: 1985 , Page(s): 617 - 621
    Cited by:  Papers (14)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    We correlate the work-function difference φps0between the polysilicon gate and the silicon substrate in an MOS system with the doping level and carrier concentration in polysilicon. Polysilicon was doped by ion implantation with arsenic and phosphorus. The doping level was varied from 1019to 1020cm-3. Hall measurements were used to determine the carrier concentration in polysilicon at a given doping level. The Hall mobility and resistivity as a function of doping level were also obtained. The work function difference φps0was determined by capacitance-voltage measurements on polysilicon-SiO2-Si capacitors with different oxide thicknesses. When plotted against the doping level, the work-function difference had a maximum at a dopant concentration of ≈ 5 × 1019cm-3, which corresponds to an electron concentration of 1.5 × 1019cm-3. At higher doping levels the value of φps0decreases. The results can not be fully understood in terms of the Si band structure. View full abstract»

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  • Gain of a heterojunction bipolar phototransistor

    Publication Year: 1985 , Page(s): 622 - 627
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    Analytical expressions have been derived for the collector current, optical gain, and quantum efficiency for a heterojunction, bi-polar phototransistor (HPT). These expressions can be utilized to optimize the current gain and quantum efficiency for HPT design. The presence of avalanche multiplication in the base-collector junction has been taken into account and shown to be a significant factor in determining the gain of an InGaAs/InP phototransistor. Experimental results of optical gain versus the collector-emitter voltage can only be explained in terms Of avalanche multiplication. View full abstract»

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  • Modeling the generation current due to donor-acceptor twins in silicon p-n junctions

    Publication Year: 1985 , Page(s): 628 - 631
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The experimental static current-voltage I-V characteristics of almost ideal silicon p-n junctions are not adequately described by the classic Sah-Noyce-Shockley theory. The I-V characteristics are accurately modeled by admitting the presence of a new class of defects in addition to Shockley-Read-Hall generation-recombination centers. The new center, modeled as a donor-acceptor twin, behaves as a pure generation center. View full abstract»

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  • The roles of the surface and bulk of the semi-insulating substrate in low-frequency anomalies of GaAs integrated circuits

    Publication Year: 1985 , Page(s): 632 - 642
    Cited by:  Papers (27)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1168 KB)  

    We investigate in detail two anomalies in metal-semiconductor field-effect transistors (MESFET) which are detrimental to their operation in a GaAs integrated circuit (IC). The first of these is side-gating and consists in a parasitic very-low-frequency transconductance between a MESFET and an isolated electrode or side gate sharing the same semi-insulating (SI) substrate. The second anomaly is kinetic and consists in a parasitic transient in the drain-source current following an abrupt change in drain-source voltage. The time constants of the transients are observed to be very sensitive to the side-gate electrode potential. The effects of different technological and operational parameters are studied. One surprising result is the very high sensitivity of side-gating to chemical wet and dry treatments and to dielectric encapsulation of the unprotected substrate surfaces. We also report low-frequency oscillations related to side-gating. Physical models are proposed and yield consistent interpretations of our experimental observations. View full abstract»

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  • A metal-gate self-aligned MOSFET using nitride oxide

    Publication Year: 1985 , Page(s): 643 - 648
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm2/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ. View full abstract»

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  • Rejection characteristics in a video-signal processor using CCD comb filters

    Publication Year: 1985 , Page(s): 649 - 653
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    This paper describes charge-coupled device (CCD) combfilter rejection characteristics in the video bandwidth. Notch-frequency shifts and rejection-ratio decreases are caused by the incomplete charge transfer in the CCD channel and also by timing error in the charge sampling, which shorten the effective delay time from the ideal 1 H period. In the 1H comb filters, 30-dB rejections are achieved within the 4.5-MHz bandwidth for less than 2 × 10-5per transfer inefficiency. The timing error in the input section can be compensated for by adjusting the input-gate biasing voltage. The analyses are extended to the 2 H comb filter constructed with three identical CCD's. The 1.2 × 10-4inefficiency, which is six times as large compared with that in the 1 H filter, is allowable to maintain the 30-dB ratio. The rejection is shown to be constant when the product of the inefficiencies in the series-connected CCD's is constant. The experimentally obtained results suggest the analyses are reasonable. View full abstract»

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  • Electron flow in the conventional X-ray tube

    Publication Year: 1985 , Page(s): 654 - 657
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    The electron-flow pattern in a conventional X-ray tube is analyzed with a ray-tracing computer program. It is shown that the emission is temperature-limited (TL) in a forward-facing sector, and space-charge-limited (SCL) in sectors on each side. The angle of the TL sector varies directly with the anode voltage and inversely with the filament temperature, generally in the range 90°-160°. The A lines of the focal spot are shown to be direct images of points near the 2 and 4 o'clock positions on the cathode, while the B lines are inverted images of points near 1 and 5 o'clock. View full abstract»

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  • The Hooge parameters of n+-p-n and p+-n-p silicon bipolar transistors

    Publication Year: 1985 , Page(s): 658 - 661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    We establish here again the fact that the Hooge parameters of NEC57807 n+-p-n and in GE82 p+-n-p silicon bipolar transistors are orders of magnitude smaller than the value 2 × 10-3postulated earlier. In the NEC57807 devices neither the base 1/ f noise nor the collector 1/ f noise is of the diffusion-fluctuation type. In the GE82 devices the collector 1/ f noise is not of the diffusion-fluctuation type, but the base 1/ f noise is of that type. We have given, also, a theory of the effects of surface recombination fluctuations in the emitter-base space-charge region on the base noise and the collector noise and find a noise spectrum that varies as I_\gamma where 0.5 < γ < 1.6 when going from small to large currents. View full abstract»

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  • Hooge parameters for various FET structures

    Publication Year: 1985 , Page(s): 662 - 666
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    We present here values for the Hooge parameters αHof various FET structures that are one or more orders of magnitude smaller than the value 2 × 10-3that was first proposed. It cannot be said for certain which of these values are due to mobility-fluctuation noise and which represent number-fluctuation noise, but it seems reasonable to assume that the lowest values of αHare more likely due to mobility fluctuations. View full abstract»

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  • A theory of the Hooge parameters of solid-state devices

    Publication Year: 1985 , Page(s): 667 - 671
    Cited by:  Papers (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    Handel's theory of quantum 1/f noise is applied to the Hooge parameters of bipolar transistors and various types of FET's. Very low values for the Hooge parameters αHnand αHpfor electrons and holes are obtained. For several cases the experimental data seem to agree with the predicted theoretical limit whereas in other cases the mobility 1/f noise is masked by other noise sources. In good GaAs devices the predicted quantum limit for αHnis reached within a factor 5-10. The theory is also applied to the Hg1-xCdxTe materials and devices. Because of the very low effective masses involved, the theory predicts values as high as 2 × 10-4-2 × 10-5, depending on x . What remains presently unexplained are the high values of αHfor semiconductor resistors and long p-n diodes. View full abstract»

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  • Optical single layer lift-off process

    Publication Year: 1985 , Page(s): 672 - 676
    Cited by:  Papers (5)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The lithography of the metal wiring layers is becoming the most confining technology in the era of VLSI (very large-scale integration), as more and more circuits have to be wired on the chip itself. The two competing technologies are subtractive etch (wet or dry), and additive metal lift-off. As lift-off needs no etching, it inherently offers cost and density advantages. It, however, requires an undercut photoresist profile. These undercuts can be achieved with an image-reversal process. The paper describes such a reversal process, especially tuned for lift-off applications. The result is a simple single-layer lift-off technology with excellent image quality. View full abstract»

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  • Resistor-loaded high-speed sense circuit for Josephson memory

    Publication Year: 1985 , Page(s): 677 - 681
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A design and experimental verification of a new high-speed sense circuit for Josephson memory are reported. This sense circuit consists of latching logic circuits with resistive loads and is able to adopt X-Y nonsequential access. It is necessary to decrease base-electrode capacitance of sense gates or to insert dummy inductors in the counter electrodes for the gate in order to realize high-speed memory circuit through word-line impedance matching. In 4-kbit RAM's, it was clarified that the gathering circuit which is composed of two-stage OR gates, each of which is composed of an 8-input wired RCL-OR gate, can minimize the gathering delay time. An experimental sense circuit was fabricated using a 5-µm Pb-alloy process, and the read-out time was measured to be about 400 ps using an on-chip sampling circuit. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego