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Electron Device Letters, IEEE

Issue 5 • Date May 1984

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Displaying Results 1 - 20 of 20
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Composite TaSi2/n+poly-Si formation by rapid thermal annealing

    Page(s): 133 - 135
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    Composite TaSi2/n+ poly-Si structures have been formed by rapid thermal annealing (RTA). Polysilicon films 0.2 µm thick were deposited on oxidized Si wafers by LPCVD and heavily doped with phosphorus by diffusion. A layer of TaSix0.22 µm thick was then cosputtered on polysilicon from separate targets. The as-deposited samples were annealed by RTA using high-intensity tungsten lamps. Uniform stoichiometric low-resistivity tantalum disilicide was formed by RTA in 1 s at 1000°C. The sheet resistance and grain size of the silicide layers are comparable to those formed by conventional furnace anneals. The surface morphology of the RTA samples is superior to that obtained by furnace annealing. These results show that RTA technique has a great potential for low-resistivity tantalum silicide formation in VLSI circuits. View full abstract»

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  • Controlled diode profiling for GaAs strip-coupled correlators

    Page(s): 136 - 138
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    Surface acoustic wave (SAW) memory correlators employ the varactor properties of Schottky diodes arrayed along the acoustic path. Described, and illustrated, here is a tailoring of the implant which defines the Schottky diode region of the strip-coupled GaAs surface acoustic wave memory correlator. The new implant schedule has resulted in improvements in correlation efficiencies in the range of 10-15 dBm for these devices compared to previously reported strip-coupled GaAs memory correlators. View full abstract»

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  • The superlattice barrier capacitor: A structure for the investigation of heterojunction interfaces

    Page(s): 139 - 141
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    A symmetric n- GaAs/AlAs-GaAs superlattice/n- GaAs structure has been fabricated and electrical measurements made between 300 and 77 K. At 238 K and below, the C-V characteristics were clearly symmetric, in good agreement with theory. Such a structure can be used as a sensitive probe of the interface defects at the "normal" and "inverted" heterojunction interfaces associated with the barrier. Furthermore, the highly nonlinear C-V characteristic of this symmetric semiconductor capacitor near-zero bias may have unique applications. View full abstract»

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  • The problem of correlating Schottky-diode barrier height with an ideality factor using I-V measurements

    Page(s): 142 - 144
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    Critical analysis is made of a recently proposed method of determining the relationship between the ideality factor and the barrier height of Schottky barrier diodes (SBD's) from I-V measurements. It is demonstrated that, while this method may produce consistent results in situations where a stable reproducible manufacturing process exists, the flat-band barrier height so determined cannot be taken to be the true flat-band barrier height. View full abstract»

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  • Accurate barrier modeling of metal and silicide contacts

    Page(s): 145 - 147
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    This letter presents a novel technique of evaluating Si consumption, dopant segregation, and pile-up effects in metal and silicide contacts on silicide using a newly developed device model based on thermionic-field emission and tunneling phenomena. The field dependence of interface charge penetration into the semiconductor is evaluated from the measured electrical characteristics of Schottky diodes and the theoretical results obtained from the model. View full abstract»

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  • Temperature dependence of hot-electron-induced degradation in MOSFET's

    Page(s): 148 - 150
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    The temperature dependence of MOSFET degradation due to hot-electron injection has been studied. The slower degradation rate at elevated temperature at fixed stressing bias follows the substrate current level which is reduced mainly by lower localized electric field rather than lower ionization coefficient (both are caused by enhanced phonon scattering). The actual degradation rate at the constant substrate current level is slightly higher at elevated temperatures, indicating an enhanced interface-state generation mechanism. This temperature dependence provides a simple relationship between device degradation and substrate current at various temperatures. View full abstract»

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  • A three-dimensional folded dynamic RAM in beam-recrystallized polysilicon

    Page(s): 151 - 153
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    A three-dimensional folded one-transistor dynamic RAM circuit consisting of an access transistor in a beam-recrystallized polysilicon layer above a storage capacitor has been fabricated. Large cell capacitance and low transistor leakage are obtained by use of multiple polysilicon layers and by folding the storage capacitor beneath the access transistor. The resulting storage times are longer than 1 min, several orders of magnitude greater than storage times in a previously published nonfolded dynamic RAM in recrystallized polysilicon [1]. View full abstract»

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  • j-MOS: A versatile power field-effect transistor

    Page(s): 154 - 156
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    A novel field-effect transistor (FET) structure that is attractive for power control applications is proposed and demonstrated. It combines MOSFET structural features and junction FET function in a simple, self-aligned structure that we refer to as j-MOS. Lateral j-MOS transistors were fabricated in silicon-on-sapphire (SOS) with on-resistance as low as 2.5 Ω in 1 cm of channel width. From this result, we project that a vertical version of j-MOS can be fabricated in silicon-on-buried insulator (SOI) with a specific on-resistance ≤ 1 m Ω.cm2, approximately a factor of two improvement over current power FET technology. View full abstract»

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  • A short-channel CMOS/SOS technology in recrystallized 0.3-µm-thick silicon-on-sapphire films

    Page(s): 156 - 158
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    CMOS/SOS devices and circuits were fabricated in 0.3-µm-thick epitaxial silicon-on-sapphire (SOS) films. Two solid-phase epitaxial recrystallization techniques double solid-phase epitaxy (DSPE) and solid-phase epitaxy and regrowth (SPEAR) reduced the total microtwin concentrations in the Si layers more than tenfold, while increasing electron and hole inversion-layer mobilities between 30 and 45 percent. Leakage currents were substantially reduced in all SPEAR devices and in n-channel DSPE transistors, with some increase observed for p-channel DSPE devices. Drive currents and subthreshold slopes also showed significant improvement in both n- and p-devices. Propagation delays below 75 ps were obtained for CMOS/SOS inverters with Loff= 0.5 µm. The application of DSPE and SPEAR techniques to 0.3-µm SOS films will extend the scaling of CMOS/SOS to circuits with VLSI complexity. View full abstract»

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  • 2-GHz 150-µW self-aligned Si MESFET logic

    Page(s): 159 - 161
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    Self-aligned normally-off silicon MESFET devices and circuits with minimum drawn gatelengths of 200 nm, and gate-to-source, and gate-to-drain spacings of 100 nm each, have been fabricated. The newly developed high-density process is based on electron beam direct writing and reactive ion etching. Ring oscillators with serial layout, a fanout of two, and drawn gatelength of 0.9 µm, show switching speeds of 220 ps at a power dissipation of 150 µW per gate. View full abstract»

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  • Evaluation of LDD MOSFET's based on hot-electron-induced degradation

    Page(s): 162 - 165
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    Hot-electron-induced device degradation in LDD MOSFET's is thoroughly studied. Conventional ways to characterize device degradation, i.e., threshold shift and transconductance reduction, are not suitable for LDD MOSFET's due to the nature of degradation in such devices. Using a current-drive degradation criterion, it is shown that LDD MOSFET's have little net advantage over conventional MOSFET's in terms of hot-electron-induced long-term degradation. View full abstract»

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  • Controlling void formation in WSi2polycides

    Page(s): 166 - 168
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    Polycides, composite wiring/electrode films formed by depositing a refractory metal silicide such as WSi2, MoSi2, or TaSi2atop a polysilicon film [1]-[4], are finding their way into IC technologies as low-resistivity electrodes/interconnects. One of the desirable features of polycide composite films is their ability for self-passivation through thermal oxidation. In some cases, however, oxidation of the two-layer materials results in the formation of large "voids" in the polysilicon film (bottom layer in the polycide) [5], [6]. A method for preventing this void formation has been found. The solution involves deposition of a thin silicon layer onto the existing two-layer material. The additional layer is designed to provide some of the silicon required for oxidation during the initial stages of self-passivation. In cases where over 200 nm of SiO2were grown atop a WSi2polycide, a silicon layer as thin as 15-nm prevented void formation. View full abstract»

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  • Submicrometer self-aligned recessed gate InGaAs MISFET exhibiting very high transconductance

    Page(s): 169 - 171
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    A new submicrometer InGaAs depletion-mode MISFET with a self-aligned recessed gate structure is presented. The techniques used to implement this FET structure are angle evaporation for submicrometer pattern definition and sputter etching/wet chemical etching for channel recess. Highest transconductance observed was in excess of 250 mS/mm, with 200 mS/mm as a more typical value. The very high transconductance is attributed partly to the low source series resistance achieved in this structure, typically 0.5 Ω.mm or less. From the IV characteristics of these FET's, a saturation velocity equal to 2.4 × 107cm/s at the drain end was deduced. View full abstract»

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  • (In,Ga)As/InP n-p-n heterojunction bipolar transistors grown by liquid phase epitaxy with high DC current gain

    Page(s): 172 - 175
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    Experimental results on heterojunction bipolar transistors made in liquid phase epitaxial (In,Ga)As and InP layers on InP substrates are described. The (In,Ga)As base layer was doped with manganese during growth and contacts were made to it by beryllium ion implantation. The maximum measured dc current gain β of these devices was in excess of 500. These devices also demonstrate for the first time in an InP-based system, the inverted emitter-down heterojunction transistor structure with a base contact, which yields a minimized collector-base junction area and should significantly improve high-frequency performance. View full abstract»

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  • A multiwafer plasma system for anodic nitridation and oxidation

    Page(s): 175 - 177
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    An experimental, high throughput and clean multiwafer system for plasma anodization is described. The applications of this system towards growing anodic silicon nitride and anodic silicon dioxide films, as well as the anodic nitridation of SiO2films are demonstrated. Pure nitride films thicker than 15 nm may be produced at 950°C. Oxide films are grown at temperature as low as 600°C. SiO2films can be converted to a high percentage of nitride by anodic treatment. View full abstract»

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  • Determining specific contact resistivity from contact end resistance measurements

    Page(s): 178 - 180
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    A method is described to determine specific contact resistivity from contact end resistance measurements using a transmission line model. A test pattern is described which minimizes the effect of current fringing around contact corners and yields an accurate determination of contact width. With this pattern, the specific contact resistivities measured on 1.3 wt % Si/Al contacts to n+ silicon junctions with different dopings show very consistent values and are independent of contact geometries. The dependence of measured specific contact resistivities on doping concentration is also in good agreement with the predictions of tunneling theory. Surprisingly, the dependence on surface concentration extends well beyond the usual range of electrically active solid solubility. View full abstract»

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  • Nonthreshold logic ring oscillators implemented with GaAs/(GaAl)As heterojunction bipolar transistors

    Page(s): 181 - 183
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    The first nonthreshold logic (NTL) ring oscillators implemented with GaAs/(GaAl)As heterojunction bipolar transistors (HBT's) are reported. Propagation delay times down to 52 ps per gate were achieved, using transistors with emitter dimensions of 1.2 µm × 5 µm. Numerical simulations of the circuits were also done, which agreed closely with the experimental results. View full abstract»

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  • Erratum

    Page(s): 184
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  • [Back cover]

    Page(s): c4
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    Freely Available from IEEE

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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