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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 1984

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Displaying Results 1 - 25 of 128
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Ultrahigh-voltage high-current gate turn-off thyristors

    Page(s): 1681 - 1686
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    High-power GTO's with ratings of 2500 V . 2000 A have been developed, and a 4500 V . 2000 A GTO was trial fabricated and performance tested, for use in traction motor control equipment. Their low ON-state voltage was attained by applying a unique anode emitter shorting structure which does not require doping of a lifetime killer such as gold to obtain suitable GTO characteristics. Their high interrupt current was obtained by introducing a ring-shaped gate structure which has uniform operation between many segments in the devices during turn-off process. View full abstract»

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  • VTinstabilities of scaled MOSFET's with the top passivation structure composed of Silicon Nitride and silicate glass films

    Page(s): 1687 - 1692
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    This paper describes the threshold-voltage instability mechanism on scaled p-channel MOSFET's with the double-layer top passivation structure composed of plasma silicon nitride and undoped silicate glass films under negative gate bias stress at high temperatures. From the results of this study, it was found that there are two kinds of instability mechanism, which have different activation energies. One mechanism, which is observed at below 200°C and is independent of the gate length, is due to the slow trapping. The other, which is observed at above 225°C is dependent on the gate length, is due to the secondary slow trapping. It is explained by the impurity diffusion followed by a reaction phenomenon. View full abstract»

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  • Optimum design of power MOSFET's

    Page(s): 1693 - 1700
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    We present a model for the on-state resistance of power vertical, double-diffused MOS (VDMOS) transistors with emphasis on cell layout optimization and supporting experimental data. Essentially the same minimum Roncan be achieved using any of six different cellular cell geometries including square and hexagonal cells. Specifically, the on-resistances of all cellular designs are essentially identical if they have the same p-well width and the same ratio of well area to cell area. Cellular designs yield lower on-resistance than linear-cell designs unless the latter, through clever layout perhaps, allows at least 1.6 times smaller well width than the former. Design examples and experiments illustrate a simple optimization procedure, which starts with choosing the minimum p-well width and depth compatible with production technology and then finding the optimum spacing between the p-wells. View full abstract»

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  • Transport study in Si-silicide-Si transistors using a Monte Carlo technique

    Page(s): 1701 - 1708
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    The Monte Carlo technique has been used for the study of electron motion in a proposed Si-silicide-Si transistor (SST). The transmission coefficient and the transit time are calculated as functions of lattice temperature, initial energy of electrons coming from the emitter, and the applied base-collector bias. The results show that a maximum transmission coefficient for electrons occurs when the initial energy exceeds the maximum energy barrier of the base-collector junction by about 0.1 eV, and the transit time decreases as the applied base-collector junction bias increases and as the temperature decreases. Space charge effects caused by operating at high current densities are shown to reduce slightly the transmission coefficient. View full abstract»

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  • Nonlinear two-dimensional impurity diffusion in semiconductors: A quasi-linear numerical analysis

    Page(s): 1708 - 1713
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    A two-dimensional numerical simulation program is proposed which enables the concentration profiles of diffused dopants in semiconductors to be calculated. This program takes the nonlinear phenomena typical of high concentrations into account; however, since the corresponding nonlinear diffusion model is made quasi-linear by means of a suitable transformation of the variable, it becomes almost as easy and efficient as a linear numerical simulation program. The numerical algorithm developed is based on the finite difference Alternating Direction Implicit (ADI) method proposed by Peaceman and Rachford. As a practical application, the two-dimensional doping profiles of arsenic into silicon are calculated for a predeposition process and for a drive-in process following an ion implantation. View full abstract»

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  • Design and performance of a low-noise charge-detection amplifier for VPCCD devices

    Page(s): 1713 - 1719
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    This paper describes the design and performance of a low-noise amplifier used with virtual phase charge-coupled devices. Topology of the detection node, details of the operation, and computer simulations for critical device parameters are presented. Attention is focused on the noise performance and charge-detection sensitivity. A simple noise model is developed and used to derive an expression for the noise equivalent number of electronsN_eewhich is then used to optimize the amplifier design. Finally, predictions obtained from the model are compared with measurements, and conclusions are drawn for the maximum attainable performance. In addition to the thermally generated noise, usually measured in buried-channel MOS transistors, an excess noise is sometimes seen at moderate to large drain biases. This phenomenon is also observed in this amplifier. However, an explanation for the effect, confirmed by measurement, is presented and a method to avoid degradation of the amplifier performance is found. View full abstract»

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  • Mathematical proof of the validity of reciprocity in one-dimensional bipolar transistors with arbitrary base parameters

    Page(s): 1720 - 1723
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    We consider the solution of the general continuity equation for the minority electrons in the base of a one-dimensional n-p-n bipolar transistor. The solution of the continuity equation can be expressed as the superposition of two linearly independent expressions. The collector current is derived as a function of these two expressions. Two cases are considered: one junction is injecting at bias VFand the other is collecting at zero bias and vice-versa. The two collector current expressions are found to be identical which confirms the reciprocity theory for the very general one-dimensional low-level injection case. View full abstract»

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  • Monte Carlo simulation of bipolar transistors

    Page(s): 1724 - 1730
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    A new approach is proposed to investigate, the limits of validity of the conventional drift-diffusion equation analysis for modeling bipolar transistor structures containing submicrometer dimensions. The single-particle Monte Carlo method is used for the solution of the Boltzmann equation. An electron velocity overshoot of 1.8 times the static saturation velocity has been found for electrons near the base-collector junction of a silicon device. The effect of this velocity overshoot was calculated to enhance the output collector current and reduce the electron transit time by 5 percent for the device structure considered in this work. View full abstract»

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  • Development of positive photoresist

    Page(s): 1730 - 1736
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    A new model is proposed to describe the development of positive photoresist over the full range of exposure. The model includes the depth dependence of development rate and is capable of fitting measured data of all resists examined to date. A measurement system for determining the exposure and development model parameters is described. Several types of photoresist and developer have been characterized under a number of processing conditions. The effect of the development model parameters on developed resist profiles is illustrated using simulation. View full abstract»

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  • Evidence of hole flow in silicon nitride for positive gate voltage

    Page(s): 1736 - 1741
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    This paper discusses the conduction mechanism of silicon nitride. n-channel transistors and MOS capacitors with the top-oxide/ nitride/bottom-oxide dielectric structure were used to characterize the dielectric conduction. Top and bottom oxides were found to have different effects on the dielectric leakage current and electron and hole tunneling. This implies that the dominant charge carriers across the top and bottom oxides are different. We claim the conduction through a bottom oxide is dominated by electron flow and conduction through a top oxide and the nitride is dominated by hole flow for positive gate voltage. Energy band diagrams are presented to discuss the effective trap level for hole conduction in the nitride and holes and electrons tunneling through the oxide/nitride/oxide dielectrics. View full abstract»

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  • Selective epitaxial growth for the fabrication of CMOS integrated circuits

    Page(s): 1741 - 1748
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    A process is described for the fabrication of CMOS integrated circuits which combines the epitaxial lateral overgrowth (ELO) technique with the concept of selective epitaxy. The resulting epitaxial material is shown to have a low defect density. Transistors fabricated in the selective epitaxy are shown to have characteristics which are a function of the epitaxial deposition conditions, the substrate orientation and dopant concentration, and the epitaxial layer thickness. Minimum device leakage currents were 250 pA/µm of channel width for n-channel devices fabricated in a p-well and 1.0 pA/µm for devices fabricated on p-substrates. The higher leakage currents for devices fabricated in a well are believed to be a result of the narrow vertical spacing (0.3-0.5 µm) between the n+source-drain regions and the n+substrate. View full abstract»

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  • A new field isolation technology employing lift-off patterning of sputtered SiO2films

    Page(s): 1748 - 1752
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    A new field isolation technology for LSI devices is described. This technology features low-temperature (<150° C) sputtered SiO2and photoresist lift-off. MOS devices are fabricated using this isolation technology. It is shown that bird's-beak-free field oxide is formed using a fabrication process which is shorter than that using other isolation methods. It is shown that the narrow-channel effect is significantly reduced in MOSFET's fabricated with this technology. View full abstract»

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  • CASFET: A MOSFET-JFET cascode device with ultralow gate capacitance

    Page(s): 1752 - 1758
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    A field-effect transistor is described that combines a short-gate MOSFET with a long-channel JFET in a cascode configuration. The composite device, a CASFET, can have a very low input capacitance due to the short gate of the MOSFET combined with the reduced Miller capacitance of the cascode. The long channel of the JFET insures that the CASFET has high output resistance. This paper discusses CASFET fabrication, performance, and modeling. View full abstract»

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  • An investigation of the effect of graded layers and tunneling on the performance of AlGaAs/GaAs heterojunction bipolar transistors

    Page(s): 1758 - 1765
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    We present the results of theoretical and experimental studies of the heterojunction bipolar transistor. Our calculations are based on a new thermionic field-diffusion model which takes into account the dependence of the emitter efficiency on the height of the interface conduction band spike and tunneling across the spike. Based on this theory we derive analytical expressions for the current-voltage characteristics and relate the short-circuit common emitter current gain to the material parameters, doping levels, grading length, and device temperature. We demonstrate that the thermoemission transport across the interface spike limits the rate of increase in the collector current with the emitter-base voltage and, as a consequence, the maximum common emitter current gain. Tunneling also plays an important role, especially for abrupt heterojunctions. Our calculations reveal an important role played by grading of the composition of the emitter region in the vicinity of the heterointerface. Such grading decreases the barrier height at the interface and greatly enhances the emitter injection efficiency. View full abstract»

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  • GaAs optoelectronic mixer operation at 4.5 GHz

    Page(s): 1766 - 1768
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    Optoelectronic heterodyne detection of high-frequency intensity modulation signals using a GaAs photoconductive mixer is reported. Flat response for optical modulation frequencies up to 4.5 GHz is observed for downconversion to a 500-MHz intermediate frequency using a low power local oscillator. Heterodyne responsivity was enhanced significantly over direct detection with the same photoconductive detector due to improved contact performance under RF bias. View full abstract»

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  • Optimization of breakdown voltage and on-resistance of VDMOS transistors

    Page(s): 1769 - 1773
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    The combined effect of the spacing between adjacent drain junctions, epilayer thickness, and resistivity in VDMOS transistors on both its breakdown voltage andR_{on} cdot Aproduct is investigated. It is shown that an increase in the breakdown voltage results as the junctions spacing is reduced. That gives a significant difference in theR_{on} cdot Aproduct when compared with results where this effect is ignored. A design optimization study is carried out to determine the parameters of a VDMOS transistor at 1000-V breakdown. View full abstract»

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  • Ideal mode operation of an InSb charge injection device

    Page(s): 1773 - 1780
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    Unlike Si or HgCdTe CID (charge injection device) arrays, which normally operate at ∼1 MHz with the presence of a ≲ 10 percent fat zero (i.e., ideal mode), current InSb CID arrays fabricated on InSb substrates can operate either at a much lower clock frequency of ∼ 10 kHz (i.e., slow charge transfer mode), or when both row and column potential wells are partially filled with a large bias charge (i.e., charge sharing mode). The slow charge transfer mode is very ineffective in reading out signal charge from a large-area array and the charge sharing mode exhibits difficulties such as reduced readout efficiency, increased line capacitance, and a large photocurrent effect. By contrast, the ideal mode is free of these problems. In this paper we describe the design and fabrication of an InSb CID array, which for the first time, successfully demonstrates the ideal mode operation. View full abstract»

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  • Breakdown voltage of a rectangular planar diffused junction with rounded corners

    Page(s): 1781 - 1783
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    Electric field distribution around the circular corners of a rectangular planar diffused junction has been analyzed with the help of three-dimensional symmetry considerations. Analytical results derived in this paper have been used in calculating the breakdown voltages of one-sided abrupt types of such planar junctions with different parameters like background doping, junction depth, and radius of curvature of the rounded corners. These results are useful in the design of planar junctions with better breakdown characteristics and optimal utilization of the semiconductor area on a wafer. View full abstract»

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  • A linear and compact charge-coupled charge packet differencer/replicator

    Page(s): 1784 - 1789
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    A new charge-coupled circuit for creating a charge packet equal to the difference of two input charge packets is analyzed. The circuit features inherent linearity through the use of quasi-three-dimensional charge-coupling, and can be implemented in a compact way. Depending upon the areal ratio of the circuit's primary electrodes, various fixed gains in the transfer characteristic may be obtained. The signal charges are transferred to the circuit through remote and possibly multiple floating diffusion collectors which may also function as summing nodes. Multiple copies of the output charge packet may be regenerated without refreshing the circuit input. A large geometry prototype device has been fabricated and characterized. The device demonstrates the operation of the circuit and features less than -40-dB linearity distortion over a dynamic range which exceeds 70 dB. Improved performance is expected in smaller geometry devices. View full abstract»

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  • Switching speed enhancement in insulated gate transistors by electron irradiation

    Page(s): 1790 - 1795
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    High-speed switching in insulated gate transistors (IGT's) has been achieved by using electron irradiation. This technique allows excellent control over the switching speed with the ability to reduce the gate turn-off time from over 20 µs to under 200 ns. This increase in speed is accompanied by an increase in the forward voltage drop during current conduction. This necessitates performing a trade-off between switching and conduction losses. Despite the increase in the forward drop, the IGT's exhibit superior characteristics in comparison with power MOSFET's and bipolar transistors up to switching frequencies of 100 kHz. View full abstract»

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  • A model for the GTO thyristor during switch-off

    Page(s): 1796 - 1803
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    A physical circuit-based model has been derived for the GTO during switch-off. The model simulates the electron-hole plasma and the depletion layer in the wide lightly doped base, and their relative motion, by application of the enthalpy method devised for modeling melting solids containing moving boundaries. Using this model, computations have been made of the power dissipation in a GTO thyristor during the tail phase of switch-off, in a typical snubber circuit, as a function of device parameters. View full abstract»

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  • Effects of injection resistance on the performance of very-short-channel MOSFET's

    Page(s): 1804 - 1808
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    Injection resistance, the spreading resistance due to current crowding at the source end of an FET channel, can lead to considerable performance reduction in short-channel MOSFET's. A simple technique for determining the magnitude of this resistance by means of measurements in the linear operation region is described. A simple analytical model which incorporates the effects of both velocity saturation and injection resistance is also developed. The method and model are experimentally verified by determination of the effects of injection resistance on MOSFET's with channel lengths from 0.2 to 24.6 µm. View full abstract»

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  • A high-transconductance self-aligned GaAs MESFET fabricated by through-AIN implantation

    Page(s): 1808 - 1813
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    This paper describes a new technique for the fabrication of high-transconductance GaAs MESFET's. Tungsten-silicide gate, self-aligned GaAs MESFET's were fabricated on extremely thin channel layers formed by implantation through AlN layers on semi-insulating GaAs substrates. Transconductance of the through-implanted MESFET's showed 30- to 50-percent increase as compared with that of conventional self-aligned MESFET's and reached its maximum value at 300 mS/mm for 1-µm gate-length FET's. The uniformity of the threshold voltage across a 2-in wafer was also excellent with a standard deviation of 44 mV. Circuit simulation indicates that the advantage of these FET's becomes more crucial when used in a very large-scale integrated circuit (VLSI). View full abstract»

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  • An analytical model for the threshold voltage of a narrow-width MOSFET

    Page(s): 1814 - 1823
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    A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology