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Electron Devices, IEEE Transactions on

Issue 6 • Date June 1984

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Displaying Results 1 - 22 of 22
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • The influence of surface charge and bevel angle on the blocking behavior of a high-voltage p+-n-n+device

    Page(s): 733 - 738
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    The breakdown voltage of p+-n-n+devices is investigated. The two-dimensional Poisson equation is solved using the finite difference method. The questions of optimal bevelling and the influence of surface charges on the blocking capability are extensively studied. Furthermore, it is investigated to replace a small bevel angle at the n+- region by a mesa-like structure. View full abstract»

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  • FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part II: Analysis

    Page(s): 739 - 746
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    An operational model is described for FCAT-II (Floating Si-gate Channel Corner Avalanche Transition-II) nonvolatile memory devices that can perform high-speed write 1 and write 0 operations with 15-V pulses of less than 50-ns duration. The distinct feature of the high-speed write 1 characteristics, including the novel write enable threshold phenomena, are quantitatively analyzed by introducing an equivalent circuit model in which the resistive floating gate over the oxide steps plays an important role as a negative resistance in the transient condition. Transient analyses of the write 1 characteristics are carried out using numerical circuit analysis. Fowler-Nordheim tunnel-governed write 0 characteristics are also evaluated and used for numerical analysis of the write 1 mode. Analytical results have quantitatively good coincidence with experimental results after introduction of a potential raising effect at the floating gate edges, as was predicted in the previous paper [1]. View full abstract»

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  • A corrugated capacitor cell (CCC)

    Page(s): 746 - 753
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    A new MOS dynamic random access memory (dRAM) cell named "CCC" has been successfully developed based on a one-device cell concept. This CCC is characterized by an etched-moat storage-capacitor extended into the substrate, resulting in almost independent increase in storage capacitance CSof its cell size. A typical CSvalue of 60 fF has been obtained with 3 × 7 µm2CCC having a 4-µm deep moat and a capacitor insulator equivalent to 15 nm SiO2in thickness. The CCC is discussed in terms of its capacitance characteristics, dRAM operation with unit 32-Kbit array, some limiting factor to its closer packing, and future considerations. View full abstract»

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  • The phase-shifting mask II: Imaging simulations and submicrometer resist exposures

    Page(s): 753 - 763
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    Submicrometer optical lithography is possible with conventional projection cameras when the mask controls the phase of the light at the object plane. Two-dimensional imaging simulations for the Mann 4800 projection camera show that the maximum spatial frequency for 60-percent contrast increases from 640 1/mm to 896 1/mm. The geometrical quality of the images of typical microcircuit patterns was shown to be acceptable for feature sizes of 0.7, 0.6, and 0.5 µ, respectively, and various parameters of the irradiance patterns were calculated. Exposures were made using a high-performance two-layer photoresist system and a mask containing patterns similar to those in the simulation. The phase-shifting mask was shown to increase exposure latitude and to produce a 95-percent yield of 833 1/mm (0.6 µ line and gap) patterns, whereas the transmission mask gave a 7-percent yield. Half micrometer features were patterned with a 22-percent yield using 0.436-µ light. View full abstract»

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  • Low-power high-speed InP MISFET direct-coupled FET logic

    Page(s): 763 - 766
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    High-dynamic-range n-channel InP MISFET direct-coupled FET logic ring oscillator and inverter integrated circuits with minimum observed propagation delay per staget_{pd} = 62ps with associated power delay product of 41 fJ and minimum observed power delay productPt_{pd} = 22fJ with associated delay of 84 ps have been fabricated on Fe-doped semi-insulating substrate material using ion implantation for contact and load channel regions and pyrolytic SiO2as the gate insulator. Accumulation-type enhancement-mode MISFET structures with source-drain separations of 1.5 µm and gate metallization lengths of 3.0 µm were employed as driver devices while both MESFET's and 1.5-µm-length ungated "velocity saturation" structures were used as loads. WithV_{DD} = 4.5V representative inverter structures exhibited logic swings of 3.58 V, noise margins of 1.00 and 0.92 V, and dc gain in the linear region of 2.2. View full abstract»

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  • A model for conduction in floating-gate EEPROM's

    Page(s): 767 - 772
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    A model of conduction between two levels of polysilicon separated by thermally grown oxide in a floating-gate EEPROM structure is described. For the model, a modified Fowler-Nordheim description of the tunnel current is used to include the effects of localized-field enhancement and localized-tunneling area. The threshold voltage as a function of time during the erase transient is derived and the degradation of the conduction efficiency with increasing write-erase cycles is modeled by extention of the model parameters to include the effects of trapped charge. Both the centroid of the charge and the parameters to describe the trap distribution with respect to the capture cross section are included. Experimental results are used to determine the model parameters and prediction of endurance and retention is discussed. View full abstract»

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  • A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

    Page(s): 773 - 784
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    A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data. View full abstract»

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  • Integral-equation solution of minority-carrier transport problems in heavily doped semiconductors

    Page(s): 785 - 792
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    The problem of minority-carrier transport in quasi-neutral regions of heavily doped semiconductors, presented in an integral-equation form, is discussed with reference to bipolar diffused-junction transistors. The procedure avoids any regional simplification of the coefficients, and builds all of them, along with the boundary conditions, into only two terms of the integral equation. This makes it easy to point out the reciprocal trade-off effects of the coefficients, particularly those deriving from the heavy doping and finite surface-recombination velocity at ohmic contacts. In addition, the integral equation can be solved by using a well-known iterative technique, the convergence of which can be determined a priori by examining the kernel. The results show that in many cases a single iteration is sufficient, yielding a closed-form expression for the minority-carrier distribution, the minority current injected into the emitter, and the emitter transparency. In those cases where the convergence is slow or fails, an alternative solution technique is suggested, based upon the expansion of the unknown into a set of orthogonal functions. View full abstract»

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  • Three-layer photoreceptor (Se-SeTe-Se) with high sensitivity in the long-wavelength region

    Page(s): 793 - 796
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    A Se-SeTe-Se three-layered photoreceptor which is highly sensitive, as well as electrically stable, in the red and near-infrared region has been developed. To improve the electrical stability without reducing the sensitivity, the SeTe layer thickness was investigated. Sensitivity for the Se(0.5 µm)-Se0.65Te0.35(0.2 µm)-Se(50 µm) layered photoreceptor is 2300 V/µJ/cm2at 660 nm, and 360 V/µJ/cm2at 800 nm. A photoreceptor drum of this layered configuration, whose sensitivity was designed for an LED light source, was very stable and exhibited high-quality printing characteristics in an LED printer. View full abstract»

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  • A two-dimensional model for the excess interstitial distribution in silicon during thermal oxidation

    Page(s): 797 - 800
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    A steady-state solution for the partial differential equation governing the two-dimensional distribution of the excess interstitials during thermal oxidation of silicon was obtained using a finite difference method. It is assumed that the excess interstitials at the unoxidizing Si-SiO2interface are annihilated at a rate proportional to the excess interstitial concentration at the interface and the surface recombination velocity of the excess interstitials. Lin et al.'s experimental observation that the lateral diffusion length of the excess interstitials under the unoxidizing Si-SiO2interface is much shorter than the vertical diffusion length in the bulk can be explained by this interface annihilation model. Surface recombination velocity divided by the bulk diffusivity of self-interstitials in silicon at the Si-SiO2interface is found to be about 0.4-1.0/µm within the oxidation temperature range between 900° and 1100°C. View full abstract»

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  • Threshold voltage scattering of GaAs MESFET's fabricated on LEC-grown semi-insulating substrates

    Page(s): 800 - 804
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    Threshold voltage standard deviation (sigma V_{th}) for MESFET's on a liquid encapsulated Czochralski (LEC) grown GaAs wafer was investigated, in connection with dislocation distribution. Threshold voltage (Vth) scattering was found to be strongly correlated to the dislocation cell network structure in the substrate. This dislocation cell network is characteristic of the LEC-grown crystal. At largesigma V_{th}region, strongly networked dislocation cell structure was observed. In the area where dislocations distributed randomly without network structure,sigma V_{th}was small in spite of high dislocation density. For FET's located in the dislocation-free region inside the network cell, low drain current Idsand high Vthwere recognized directly by a curve tracer. The experimental results regarding the dislocation network effect on Vthscattering are discussed along with cathodoluminescence study results. View full abstract»

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  • Optoelectronic integrated device with light amplification and optical bistability

    Page(s): 805 - 811
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    With the use of InP compound and InGaAsP alloy semiconductors, integrated devices have been fabricated in which a double heterojunction light-emitting diode is integrated onto the collector portion of a heterojunction phototransistor. The following results have been achieved in experiments with 1.15-µm wavelength light. The device amplifies the light. The maximum gain was 11.2 and the maximum differential was 31. The device is optically bistable. The optical bistability with positive gain was operated with at most 40-µW input light. The device exhibits a function similar to a light-activated thyristor and possesses a light unidirectional function. The unidirectionality measured was 16.5 dB. View full abstract»

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  • InGaAsP/InP wavelength-selective heterojunction phototransistors

    Page(s): 812 - 817
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    High-gain phototransistors with narrow spectral response (wavelength-selective phototransistors) have been developed by adding an absorption layer to a wide-bandgap heterojunction phototransistor using the InGaAsP/InP material system. The spectral response peaks at approximately 1.2 µm and the spectral half-width of 53 nm is achieved. This device exhibited an optical gain as high as 400 at the peak wavelength under an incident light power Pinof 3.6 µW. The rise time was measured to be 18 µs at Pin= 10 µW. The noise characteristic was also measured for this device, and the resultant detectivity D*was estimated to be 3.7 × 1010cm . Hz1/2/W at a frequency of 2 kHz under an optical bias level of 0.1 µW. These characteristics have been theoretically discussed in detail. View full abstract»

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  • A large-area power MOSFET designed for low conduction losses

    Page(s): 817 - 820
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    A new power MOSFET has been fabricated that conducts 75 A with an on-state resistance of 0.012 Ω and blocks 60 V. The device may be used as a low-loss synchronous rectifier in efficient high-frequency power supplies or as a high-current power switch in applications such as emitter switching. The device design criteria include obtaining the largest possible fraction of the ideal blocking voltage and obtaining the minimum on-State resistance. Efficient utilization of the device area requires smaller feature size and shallower junction depths for low-voltage power MOSFET's than for high-voltage ones. The device reported on is 300 mils on a side and contains over 60 000 MOSFET cells in parallel. It has a gate width of more than 4 m. This device is larger and more complex than any previously reported power MOSFET. It provides an example of how power device processing techniques are approaching those of LSI circuit technology. View full abstract»

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  • The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

    Page(s): 821 - 828
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    A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs. View full abstract»

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  • A new aluminum pattern formation using substitution reaction of aluminum for polysilicon and its application to MOS device fabrication

    Page(s): 828 - 832
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    This paper describes a new aluminum pattern formation process using the substitution reaction of aluminum for polysilicon (APSP), and its application to the fabrication of self-aligned aluminum-gate MOSFET's. The APSP method uses the intensive interdiffusion reaction between aluminum and polysilicon observed for contact structure where the aluminum film overlaps polysilicon and is heat treated below the eutectic temperature (577°C). The basic idea in the fabrication of self-aligned aluminum-gate MOSFET's using APSP is to replace the polysilicon gate with an aluminum gate in the final step following fabrication of the self-aligned polysilicon-gate MOSFET. It is shown that the new fabrication process can be followed by almost all of the conventional polysilicon-gate processes. It is also shown that the electrical characteristics of the aluminum-gate MOSFET fabricated using APSP are nearly the same as those of polysilicon-gate MOSFET's fabricated on the same wafer. View full abstract»

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  • Charge injection transistor based on real-space hot-electron transfer

    Page(s): 832 - 839
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    We describe a new transistor based on hot-electron transfer between two conducting layers separated by a potential barrier. The mechanism of its operation consists of controlling charge injection over the barrier by modulating the electron temperature in one of the layers. This physical principle is different from those employed in all previous three-terminal amplifying devices-which are based either on the modulation of a potential barrier (vacuum triode, bipolar transistor, various analog transistors) or on the modulation of charge in a resistive channel (field effect transistors). In contrast to this, the present device can be compared to a hypothetical vacuum diode whose cathode has an effective electron temperature which is controlled without inertia by an input electrode ("cathode heater"). The device has been implemented in an AlGaAs/GaAs heterojunction structure. One of the conducting layers is realized as an FET channel, the other as a heavily doped GaAs substrate. The layers are separated by an AlxGa1 - xAs graded barrier. Application of a source-to-drain field leads to a heating of channel electrons and charge injection into the substrate. The substrate thus serves as an anode and the FET channel represents a hot-electron cathode, whose effective temperature is controlled by the source-to-drain field. Operation of the charge injection transistor is studied at 300, 77, and 4.2 K. At 77 K the existence of power gain is demonstrated experimentally with the measured value of the mutual conductance gmreaching 280 mS/mm (at 300 K, gm≈ 88 mS/mm). The fundamental limit on the device speed of operation is analyzed and shown to be determined by the time of flight of electrons across a high-field region of spatial extent ∼ 10-5cm. Practical ways of approaching this limit are discussed. The process of hot-electron injection from the channel is studied experimentally at 77 and 4.2 K with the purpose of measuring the electron temperature in the channel at different bias conditions. For not too high substrate bias the electron temperature in the channel is found to be proportional to the square of the heating voltage. View full abstract»

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  • A new self-aligned recessed-gate InP MESFET

    Page(s): 840 - 841
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    We describe a new self-aligned recessed-gate InP MESFET. In this structure, material selective and anisotropic etching properties of InP/InGaAsP system are utilized to alleviate the difficulties associated with channel recess and gate alignment. Using this technique a 1-µm Al-gate InP MESFET with a transconductance ∼ 110 mS/mm is demonstrated. View full abstract»

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  • Stripe geometry InP/InGaAsP lasers fabricated with deuteron bombardment

    Page(s): 841 - 843
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    Stripe geometry gain-guided InP/InGaAsP lasers have reproducibly been fabricated with deuteron bombardment. Good electrical isolation was observed in 250-µm-long laser chips, and CW thresholds as low as 105 mA have been achieved. View full abstract»

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  • Errata

    Page(s): 843
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    Freely Available from IEEE
  • [Back cover]

    Page(s): c4
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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Georgia Institute of Technology