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Electron Devices, IEEE Transactions on

Issue 4 • Date April 1984

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Displaying Results 1 - 21 of 21
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

    Page(s): 401 - 408
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    A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated. View full abstract»

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  • Method for determining the emitter and base series resistances of bipolar transistors

    Page(s): 409 - 412
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    A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the idealexp (qV_{BE}/kT)behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors. View full abstract»

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  • Measurement of diffusion length, lifetime, and surface recombination velocity in thin semiconductor layers

    Page(s): 413 - 416
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    A small-signal admittance method is developed for the determination of two important parameters affecting the performance of several semiconductor devices with thin layers such as I2L and MOS transistors, OCI-HLE, BSF and TJ solar cells. These parameters, the minority-carrier diffusion length (or the minority-carrier lifetime) and the surface recombination velocity, are found using a combination of low-frequency and high-frequency admittance measurements. The theoretical base of the method and experimental results showing its application and usefulness are presented. View full abstract»

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  • A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET

    Page(s): 416 - 420
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    A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm × 3.5 mm transistor. This chip had an on-resistance of 2.3 Ω and a 500-V source-drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively. View full abstract»

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  • Proton damage in GaAs solar cells

    Page(s): 421 - 422
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    A simplified model for the short-circuit current reduction caused by proton-induced radiation damage is described. The model accounts for the nonuniformity of defect production within heteroface GaAs shallow junction solar cells. The results from the model show agreement with the strong energy dependence observed in proton radiation damage experiments. View full abstract»

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  • Channel potential and channel width in narrow buried-channel MOSFET's

    Page(s): 423 - 429
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    A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results. View full abstract»

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  • Spectral response of n+-n-p and n+-p photodiodes

    Page(s): 430 - 434
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    Results of calculations for the quantum efficiency of three different types of n+-p, n+-n-p, and OCI-HLE diodes are reported. Exact numerical modeling of current density equations, modified to include bandgap reduction and Auger recombination is used to compute the quantum efficiency of these diodes. It is found that an optimized n+-p structure can result in over all spectral response comparable to the n+-n-p structure, although it is not as good as that of the OCI-HLE type of diodes. Further, these calculations show that one can achieve low dark current in these diodes, but at the expense of lower quantum efficiency particularly for wavelengths less than 0.4 µm. View full abstract»

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  • Improvement in GaAs MESFET drain conductance by a steplike-gate structure

    Page(s): 435 - 439
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    A new steplike-gate GaAs MESFET structure, having a low drain conductance in comparison with a conventional recess structure, is presented. In order to reduce the drain conductance, the device design parameters related to gate structures are optimized using a two-dimensional device simulator. Experimental results obtained from fabricated devices, based on these optimized device parameters, show excellent low drain conductance characteristics. The reduced drain conductance can improve the maximum available gain in high-frequency GaAs analog integrated circuits. View full abstract»

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  • Dominant subthreshold conduction paths in short-channel MOSFET's

    Page(s): 440 - 447
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    Conduction modes in off-biased n+-polysilicon gate MOSFET's of both polarities have been analyzed by two-dimensional device simulations. It was found that the dominant leakage paths in p-channel and n-channel enhancement devices occur in the bulk and at the surface, respectively, atV_{GS} = V_{BS} = 0. The control of these two distinct modes is the flatband voltage of the gate. The situation is exactly reversed when boron-doped polysilicon is used as the gate. Additionally, we showed that this physical insight can be readily gained by a quasi-two-dimensional analysis of the surface potential and its bending into the substrate. The leakage mode in short-channel MOSFET's with other gate material or with different interface properties generated by radiation or other stresses can thus be easily assessed. Subthreshold characteristics have been simulated for n+-polysilicon-gate low-threshold p-channel transistors having a p-type surface from boron counterdoping. The computed channel-length dependence is found to be in good agreement with measured data. Dominant leakage paths, in this case, remain in the bulk, while the surface holes from boron counterdoping are depleted by the flatband voltage. Since the common practice for reducing subthreshold leakage is to enhance substrate impurity concentration where punchthrough occurs, we therefore conclude that different strategies of process tailoring are required for MOSFET's of different gate material, surface polarity, and interface properties. View full abstract»

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  • Principles of operation of short-channel gallium arsenide field-effect transistor determined by Monte Carlo method

    Page(s): 448 - 452
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    The electrical properties of a GaAs FET having a practical doping density and having a quarter-micrometer source-drain distance and a quarter-micrometer gate length have been studied by two-dimensional Monte Carlo particle simulation.I_{ds} = 3.3mA/20µm,g_{m} = 600mS/mm, andf_{T} = 160GHz are predicted. The reasons for the high performances are discussed in terms of the electron dynamics in the device. The current saturation mechanism and the current control mechanism of the FET are made clear. View full abstract»

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  • Generalized scaling theory and its application to a ¼ micrometer MOSFET design

    Page(s): 452 - 462
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    In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved. View full abstract»

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  • Recombination lifetime using the pulsed MOS capacitor

    Page(s): 462 - 467
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    The pulsed MOS capacitor is routinely used to measure the generation lifetime. A new technique is described here in which the same device is used to obtain the recombination lifetime. The measurement technique is identical to the commonly used pulsed C-t method except that the device is operated at an elevated temperature of 70- 100°C, where quasi-neutral current originating below the space-charge region dominates over space-charge region currents. The new technique, coupled with established techniques, makes possible the simultaneous determination of τgand τr. View full abstract»

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  • Modeling and characterization for high-speed GaAlAs-GaAs n-p-n heterojunction bipolar transistors

    Page(s): 467 - 473
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    A numerical one-dimensional model is employed to predict dc and switching characteristics for n-p-n type GaAlAs-GaAs transistors, including heteroemitter-homocollector and heteroemitter-heterocollector junction structure, where four kinds of doping profiles are considered. Also, Si and GaAs homojunction transistors are referred to for comparison. Switching performance is discussed for a single unit case, with and without a base resistance, and for a DCTL-type two-stage inverter case, including the delay time dependence on fanout. View full abstract»

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  • Large-signal theory of a two-stage wideband gyro-TWT

    Page(s): 474 - 480
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    A self-consistent large-signal theory is used to obtain gain and efficiency of the two-stage tapered gyro-TWT in a nonuniform external magnetic field. Calculations show that it is possible to design a device having 45 percent bandwidth at 45-dB gain and 25 percent efficiency if the axial velocity spread of the beam electrons is zero. It is found that the gain and bandwidth are very sensitive to the degree of beam velocity spread, the external magnetic field profile, and the various beam and circuit parameters. We also derive an expression for the efficiency under quasi-linear approximation in order to get a physical understanding of the device performance. View full abstract»

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  • Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system—Part I: Small signal theory

    Page(s): 480 - 493
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    A theory of conduction in polycrystalline silicon is presented. The present approach fundamentally differs from previous theories in its treatment of the grain boundary. This theory regards the grain boundary as amorphous semiconductor in equilibrium contact with crystalline grain. The model explains the electrical properties of polysilicon in terms of the electronic and structural parameters of the material and is in excellent agreement with the experimental data. The formulation is applicable for arbitrary grain size, temperature, doping concentration, and applied voltage. Specifically, the temperature dependence of resistivity is explained in terms of conduction channels inherent in the amorphous grain boundary. Also, this paper explicitly compares the previous emission theories with the present model in terms of voltage partition scheme and I - V predictions. View full abstract»

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  • Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system—Part II: General I-V theory

    Page(s): 493 - 500
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    A general model for conduction in polysilicon is presented for arbitrary applied voltage. The model incorporates the effect of mobile carrier redistribution under bias and accounts for the high field switching in amorphous grain boundary. Microscopic mobilities used for describing the carrier transport provides a physical basis for introducing the grain voltage across the unit cell of polysilicon. The voltage, in turn, distributes itself to preserve a constant current density therein. This new criterion yields a new voltage partitioning scheme, and a general expression for the corresponding current is derived in terms of pertinent system parameters. View full abstract»

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  • Deep levels at p-n and n-p AlGaAs-GaAs heterojunction interfaces

    Page(s): 500 - 505
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    Forward current-voltage measurements and DLTS spectra were obtained for p--n and n--p Al0.3Ga0.7As-GaAs heterodiodes. The current-voltage measurements support a tunneling current model for the p--n diodes and a diffusion-recombination current model for the n--p diodes. No deep levels were observed for the p--n structure, but two new levels at about 0.1 and 0.4 eV below the conduction band edge, and possibly zinc related, were found in the n--p devices. View full abstract»

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  • A simplified capless annealing of GaAs for MESFET applications

    Page(s): 506 - 508
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    A simple capless annealing technique for post-implantation annealing of a GaAs wafer is described. The technique incorporates a novel boat design and uses InAs as the source of arsenic overpressure. Using this technique, wafers annealed at 850°C show mobilities in the range of 4000 cm2. V-1. S-1with over 85-percent activation for a Si dose of5 times 10^{12}cm-2. Dopant depth profiles with peak donor densities of2 times 10^{17}cm-3and minimal tailing were demonstrated. Electron channeling data show that crystallinity is fully restored during the anneal. 1-µm gate length MESFET's processed on n+-n implanted layers exhibitedg_{m} geq 160mS/mm and pinchoff voltages in the range of 3 V. View full abstract»

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  • The influence of different insulators on paladium-gate metal-insulator-semiconductor hydrogen sensors

    Page(s): 508 - 510
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    It has previously been shown that the hydrogen induced drift problems of palladium-gate metal-oxide-semiconductor hydrogen sensors can be eliminated. This was achieved through the introduction of a thin thermally oxidized alumina layer between the Pd metal gate and the silicon dioxide. We show that sputtered metal oxides such as alumina, tantalum pentoxide, and LPCVD silicon nitride have similar effects on the hydrogen induced drift. View full abstract»

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  • [Back cover]

    Page(s): c4
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology