IEEE Electron Device Letters

Issue 7 • July 1983

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  • [Front cover and table of contents]

    Publication Year: 1983, Page(s): c1
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    Freely Available from IEEE
  • Substrate influence on NMOS transistors in large-area laser crystallized isolated Si layers

    Publication Year: 1983, Page(s):205 - 207
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Metal-gate NMOS transistors have been fabricated in isolated silicon layers prepared in high-temperature biased laser crystallization. The transistor parameters are strongly influenced by the substrate material, in our case simultaneously processed silica and silicon wafers. Stress built up in the silicon layer strongly affects the carrier mobility and may also significantly influence the threshol... View full abstract»

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  • Characterization of tantalum-silicon films on GaAs at elevated temperatures

    Publication Year: 1983, Page(s):207 - 209
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    RF sputter-deposited tantalum-silicon films on GaAs have been investigated using four-point probe, glancing-angle X-ray diffraction, Auger electron spectroscopy, and MeV4He+backscattering spectrometry as a function of annealing up to 850°C. Experimental results show that: 1) there is no observable Ta or Si migration from the TaSi2overlayer into the GaAs substr... View full abstract»

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  • Fabrication of submicrometer gold lines using optical lithography and high-growth-rate electroplating

    Publication Year: 1983, Page(s):210 - 212
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    This letter presents a process for fabricating submicrometer gold lines with high aspect ratio and vertical sidewalls using high-growth-rate (133-nm/min) electroplating. A two-resist-layer system, photolithography, angled evaporation, and dry etching techniques are used to fabricate the electroplating mask. Lines less than 0.2 µm wide, with aspect ratios greater than 5, are obtained with the ... View full abstract»

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  • All-binary AlAs—GaAs laser diode

    Publication Year: 1983, Page(s):212 - 214
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Thin layers of AlAs and GaAs, grown by molecular beam epitaxy (MBE), are used to simulate the properties of AlxGa1-xAs. These AlAs-GaAs superlattices (SL's) are used as cladding layers (instead of AlxGa1-xAs) in heterostructure lasers capable of room-temperature operation. It is thus possible to obtain laser diodes which are composed only of the binary c... View full abstract»

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  • High-speed logic at 300K with self-aligned submicrometer-gate GaAs MESFET's

    Publication Year: 1983, Page(s):215 - 217
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The fastest room-temperature logic gate operation yet reported has been achieved with an improved technology for self-aligned ion-implanted GaAs MESFET's. The procedure involves fabrication of 0.75/0.6-µm "T-gate" structures using electron-beam lithography, and employs arsenic-overpressure capless annealing of the self-aligned n+-implant. Minimum propagation delays of 15.4 ps/ stag... View full abstract»

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  • Annealing effects of NTD silicon for semiconductor power devices

    Publication Year: 1983, Page(s):218 - 220
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The use of neutron transmutation doped (NTD) Si has become very important for processing high-voltage power devices. A simple annealing process is usually required to anneal the lattice defects caused by neutron irradiation. This is usually performed by the silicon supplier by annealing the silicon crystal at a low temperature (approximately 700°C). High-voltage power devices, however, requir... View full abstract»

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  • Limitations of quasi-static capacitance models for the MOS transistor

    Publication Year: 1983, Page(s):221 - 224
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This letter compares the Meyer [1] and Ward [2,3] quasi-static, intrinsic capacitance formulations for the MOS transistor to an exact, non-quasi-static, incremental analysis of a simplified device. This analysis yields an incremental admittance matrix for the device whose terms are ratios of power series. The Meyer and Ward models are shown to be approximations to this exact solution. Experimental... View full abstract»

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  • Super-gain silicon MIS heterojunction emitter transistors

    Publication Year: 1983, Page(s):225 - 227
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Silicon bipolar transistors are described with common emitter current gains approaching 25 000, believed to be the highest ever reported for a bipolar device. A heterojunction emitter structure based on a tunneling metal-thin insulator-semiconductor (MIS) contact in conjunction with a shallow implanted base region is responsible for this improved performance. The significance of this result lies i... View full abstract»

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  • A lateral metal—insulator—p-Si tunnel transistor

    Publication Year: 1983, Page(s):228 - 230
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a h... View full abstract»

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  • Transient annealing of indium phosphide

    Publication Year: 1983, Page(s):231 - 233
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    Thermal treatment of semiconductor samples in the range ∼ 650 to 900°C is an integral part of planar device processing for the activation of implanted ion species. This letter describes a rapid annealing procedure for the short-term treatment of such implants, which from data obtained on InP is seen to result in high activation efficiencies and mobilities ∼ 85 percent and 2600 cm<... View full abstract»

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  • High-density and reduced latchup susceptibility CMOS technology for VLSI

    Publication Year: 1983, Page(s):233 - 235
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Increasing layout density and reducing susceptibility to latchup are two of the most pressing concerns in making CMOS a superior VLSI technology. This work presents a possible solution to these CMOS issues. Significant reductions of the well (in our case p-well) resistance and of the well side diffusion are the results of the incorporation of a heavily doped epitaxial buried layer in the CMOS proc... View full abstract»

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  • Analysis of the channel inversion layer capacitance in the very thin-gate IGFET

    Publication Year: 1983, Page(s):236 - 239
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (403 KB)

    As the gate insulator thickness approaches the channel thickness, the gate capacitance is speculated to be smaller than its gate insulator capacitance. The gate capacitance of the thin-gate IGFET is calculated using Maxwell-Boltzmann and Fermi-Dirac statistics and is experimentally measured. The results show that the gate capacitance approaches the gate insulator capacitance regardless of the gate... View full abstract»

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  • Linear-region conductance of thin-film SOI MOSFET's with grain boundaries

    Publication Year: 1983, Page(s):239 - 242
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The linear-region conductance of silicon-on-insulator (SOI) MOSFET's is modeled by properly combining theoretical descriptions of the effects of grain boundaries in the channel region and of charge coupling between the front and back gates. The model is supported by measurements of thin-film SOI MOSFET's with and without grain boundaries. The theoretical-experimental analysis clearly distinguishes... View full abstract»

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  • Fabrication of nanometer metal structures by a combination of techniques of metal evaporation and E-beam nanolithography

    Publication Year: 1983, Page(s):243 - 245
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A simple but effective technique is described in which a multiple strand filament source for thermal evaporation of metals is used in conjunction with e-beam nanolithography. It is capable of fabricating nanometer metal structures with dimensions smaller than the resist opening by e-beam nanolithography. Preliminary results presented in this paper illustrate that this technique can be extended to ... View full abstract»

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  • Gate-field-induced carrier heating in Si MOSFET's

    Publication Year: 1983, Page(s):246 - 248
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    We have used Si MOSFET's to study the variation of the channel Hall mobility and noise temperature with the gate voltage. From the Hall mobility measurements, a new empirical expression is found to describe the mobility degradation with gate voltage over a wide range of transverse electric field. By measuring the thermal noise, it is found that the channel carriers appear to be heated by the gate ... View full abstract»

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  • Hot-electron currents in very short channel MOSFET's

    Publication Year: 1983, Page(s):249 - 251
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier f... View full abstract»

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  • In0.53Ga0.47As submicrometer FET's Grown by MBE

    Publication Year: 1983, Page(s):252 - 254
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    We describe the fabrication process for InGaAs submicrometer gate JFET's, using Be ion implantation and wet chemical etching. A gate length as small as 0.5 µm can be formed by this technique. Such FET's made on MBE-grown material bad a dc trans-conductance as high as 85 mS/mm and showed a high power-handling capability. View full abstract»

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  • Al/Poly Si specific contact resistivity

    Publication Year: 1983, Page(s):255 - 257
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Experimental results on the specific contact resistivity of Al/polysilicon are given for Al/1.5-percent Si contacting poly Si implanted with boron or phosphorus, annealed to surface concentrations from 3E18 to 4E20 cm-3. Specific contact resistivities of the interfaces involved were determined using an extrapolation method. Measurements were taken at room temperature, and were conducted... View full abstract»

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  • [Back cover]

    Publication Year: 1983, Page(s): c4
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    Freely Available from IEEE

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Editor-in-Chief

Tsu-Jae King Liu
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