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IEEE Electron Device Letters

Issue 9 • Sept. 1982

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Displaying Results 1 - 13 of 13
  • [Front cover and table of contents]

    Publication Year: 1982, Page(s): c1
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    Freely Available from IEEE
  • Safety drain voltage avoiding avalanche breakdown in MOSFET

    Publication Year: 1982, Page(s):245 - 247
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB)

    It has been found that the avalanche breakdown voltage of MOSFET is independent of substrate bias and increases linearly with gate voltage in an operation regime. Applying this body-effect independency of breakdown, we obtain a maximum safety drain bias, below which avalanche breakdown is completely avoided. This safety drain voltage can be expressed in an empirical form ofgL_{eff}^{nu}... View full abstract»

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  • Long-term transient radiation-resistant GaAs FET's

    Publication Year: 1982, Page(s):248 - 250
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The amplitude of long term, pulse-radiation-induced transients in ion implanted GaAs FET's has been reduced by up to two orders of magnitude by the addition of a deep buried p-layer beneath the active n-layer. The p-layer was formed by ion implantation of Be to depth of 0.8 µm below the Si implanted n-active channel. Backgating was also greatly reduced as indicated by a much smaller amplitude... View full abstract»

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  • Estimation of doping profiles in short channel MOSFET's using DC Measurements

    Publication Year: 1982, Page(s):250 - 253
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Estimation of impurity profiles in short channel enhancement-mode MOSFET's using the dc measurement technique is studied. The use of long channel theory predicts erroneous impurity profiles for devices with channel lengths of less than 6 µm. A new empirical model for substrate charge sharing is presented which provides good agreement between profiles estimated by measurements on identically d... View full abstract»

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  • Electrically amplified optical recording

    Publication Year: 1982, Page(s):254 - 255
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    We describe a new optical recording geometry which reduces the laser power required to record micrometer size spots to 0.1 mW in the power limited regime. This is achieved by shifting the power burden from the laser to a voltage source which is connected across a thin-film transparent conductor-photoconductor-conductor sandwich. The sharply focused laser beam switches the photoconductor to a low r... View full abstract»

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  • Fully ion implanted InP junction FET's

    Publication Year: 1982, Page(s):256 - 258
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (590 KB)

    This article reports on the fabrication and performance of all ion implanted, 1.0 µm gate length, InP junction field-effect transistors (JFET's). Device fabrication includes the use of multiple energy Si implantation, selective Be implantation, proximity annealing, and Cl2plasma etching. The observed 25 V gate-source breakdown voltage is shown, byC-Vand SIMS analysis, to... View full abstract»

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  • Determination of lifetime and diffusion length in silicon solar cells by self-biased (photovoltage) capacitance measurements

    Publication Year: 1982, Page(s):259 - 261
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Many methods have been developed for the measurement of the diffusion length and lifetime of minority carriers in p-n junction solar cells. This paper presents a new technique for the measurement of these parameters, based on capacitance measurements in forward-bias condition at room and liquid air temperatures. In this experiment the solar cell was not biased by an external dc source, but was for... View full abstract»

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  • Electronically adjustable delay for Josephson technology

    Publication Year: 1982, Page(s):261 - 263
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    An electronically adjustable time delay circuit for superconducting technology is reported. In conjunction with a superconducting sampler on the same chip, the delay circuit has allowed measurement of waveforms with an apparent resolution of 8.5 ps. The delay circuit permits flicker-free oscilloscope displays of fast waveforms, and provides the circuitry needed for further speed advances in superc... View full abstract»

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  • A novel low-power static GaAs MESFET logic gate

    Publication Year: 1982, Page(s):264 - 267
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved. View full abstract»

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  • Dynamic packet splitting in charge domain devices

    Publication Year: 1982, Page(s):268 - 270
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A set of experiments has been designed to investigate techniques for improving the accuracy of charge packet splitting using field oxide barriers. These experiments studied the effect of channel width (250 µm, 500 µm), split ratio (1:1, 1:3, 1:9), and "dummy" splitters (to equalize lateral fields) on split accuracy. In general, it was observed that split accuracy is higher in wider chann... View full abstract»

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  • 101-Stage 2 µm gate ring oscillators in laser-grown silicon islands embedded in SiO2

    Publication Year: 1982, Page(s):270 - 272
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (645 KB)

    E/D MOS test transistors and 101-stage 2 µm gate E/D MOS ring oscillators were fabricated in laser-grown single- and multicrystal islands embedded in oxide substrates. Most transistors showed goodI-Vcharacteristics, short-channel effects, and kink effects. Ring oscillators had a switching delay per stage (τPd) of 0.4 ns and a power-delay product (τ_{Pd} mi... View full abstract»

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  • Erratum

    Publication Year: 1982, Page(s): 272
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  • [Back cover]

    Publication Year: 1982, Page(s): c4
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    Freely Available from IEEE

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Editor-in-Chief

Tsu-Jae King Liu
tking@eecs.berkeley.edu