By Topic

Electron Devices, IEEE Transactions on

Issue 9 • Date Sept. 1981

Filter Results

Displaying Results 1 - 25 of 25
  • [Front cover and table of contents]

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (211 KB)  
    Freely Available from IEEE
  • Announcements

    Page(s): 991 - 992
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Subthreshold conduction in silicon-on-sapphire transistors

    Page(s): 993 - 1002
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    The subthreshold conduction in silicon-on-sapphire MOS transistors has been studied both theoretically and experimentally. A simple model to describe the subthreshold conduction current for both thick films and thin films is derived in terms of charges in the silicon and charges at the silicon-silicon dioxide and silicon-sapphire interfaces. The model has been extended to cover short-channel transistors by application of charge conservation under the channel region. It is shown that the subthreshold conduction current for a SOS-MOS transistor has a form similar to that found in bulk transistors, but with modification of the terms due to the finite silicon film thickness and the unique geometry of the SOS-MOS transistor. The general form of the model has been confirmed by measurement of the subthreshold current on several hundred SOS-MOS transistors of different geometries manufactured by various companies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A study of Pd/Si MIS Schottky barrier diode hydrogen detector

    Page(s): 1003 - 1009
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    Pd/Si MIS Schottky diode hydrogen detectors have been fabricated with a response of 2-3 orders of magnitude change in current for 154 ppm of H2in N2. Detailed evaluation of dark I-V, C-V, illuminated I-V, and internal photoemission data unambiguously ascribes the strong hydrogen sensitivity of these diodes to hydrogen-induced change in the work function of Pd, rather than to any surface-state effects. The reaction rate of the device to different gas ambients has been studied with time response measurements. A long-term degradation mechanism has been identified and traced to the poisoning of Pd by environmental sulfur. The role of oxygen and atomic hydrogen in determining the Schottky barrier height also is discussed in some detail. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

    Page(s): 1010 - 1013
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd2Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL (FI = FO = 1) circuits and 1.3 ns at 0.15 mA for the MTL (FO = 4) circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The platinum doped MOST: A memory storage element

    Page(s): 1014 - 1017
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The effect of diffused platinum on MOSFET's has been studied. The materials used were View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analytic model for minority-carrier transport in heavily doped regions of silicon devices

    Page(s): 1018 - 1025
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    A simple analytic description of the minority-carrier current injected into typical diffused (or ion-implanted) heavily doped regions of silicon bipolar devices is derived. The effects of energy-bandgap narrowing, majority-carrier degeneracy, Auger recombination, a doping-density gradient, and surface recombination are accounted for tractably by using key approximations. Numerical solutions of the minority-carrier continuity equation support the model and facilitate the evaluation of the model parameters, which follow directly from the doping-density profile. The accuracy of the model is within the bounds of uncertainty emanating from present equivocal characterizations of bandgap narrowing and of Auger carrier lifetimes. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Threshold voltage characteristics of depletion-mode MOSFET's

    Page(s): 1025 - 1030
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    This paper presents the results of a study of the characteristics of the depletion-mode MOSFET. In particular, it is shown that the threshold voltage of this device is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel. The effect of these impurities on the short channel behavior of the devices also is examined. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low noise ion-implanted InP FET's

    Page(s): 1031 - 1034
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    Ion-implanted one micron gate length InP FET's are described with noise figures as low as 3.5 dB at 12 GHz. This is the lowest published noise figure for InP FET's. The InP FET microwave performance data are compared with those of equivalent geometry GaAs FET's with either ion implanted or epitaxial channels. Microwave results indicate a definite gain advantage of InP FET's over these GaAs counterparts. Noise figures of both types of FET's are comparable but InP substrate improvement and implant profile optimization are suggested as a means of further reduction of the noise figure of InP FET's. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Coplanar gas-discharge display

    Page(s): 1035 - 1042
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    The electric field strength between coplanar electrodes is calculated employing "conformal transformations." The electron multiplication factor is then computed in the nonuniform field region. These calculations have been made for different gap lengths, voltages, and also for different gases and gas pressures. The configuration results in a curved discharge path. It is found that the electron multiplication is maximum along a particular flux line and the prebreakdown discharge is expected to follow this flux line. Experimental tubes incorporating several coplanar gaps have been fabricated. Breakdown voltages have been measured for various discharge gaps and also for various gases such as xenon, helium, neon, argon, and neon-argon mixture (99.5:0.5) at different filling pressures. The variation of breakdown voltage with pressure and gap length is discussed. The observed discharge paths are curved and this is in agreement with theoretical results. A few experimental single-digit coplanar gas-discharge displays (CGDD's) with digit height of 5 cm have been fabricated and dependence of their characteristics on various parameters, including spacing between top glass plate and bottom substrate, have been studied. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Numerical analysis of turn-off characteristics for a gate turn-off thyristor with a shorted anode emitter

    Page(s): 1043 - 1047
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    Turn-off current waveform for a gate turn-off thyristor (GTO) with a shorted anode emitter has been calculated numerically by solving the semiconductor basic equations in an equivalent one-dimensional model device. This model is derived from the analysis of current and carrier distributions obtained by a two-dimensional calculation of the on-state of GTO. A calculated turn-off current waveform agrees well with the experimental waveform. The computational time of one case is about 2 min. It is shown that this one-dimensional analysis method is useful for the calculation of the turn-off time. Using this one-dimensional model during the turn-off process and the two-dimensional model in the on-state, the relation between turn-off time and the forward voltage drop can be obtained in relation to the shorted emitter structure. It is shown that the shorted emitter structure is useful to improve this tradeoff relation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dual-electron-injector-structure electrically alterable read-only-memory modeling studies

    Page(s): 1047 - 1053
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    The threshold voltage shift of various dual-electron-injector structures (DEIS's) which are composed of chemically vapor-deposited (CVD) stacks of Si-rich SiO2, SiO2, and Si-rich SiO2incorporated into floating polycrystalline-silicon-gate electrically alterable read-only memories (EAROM's) has been studied as a function of write/erase voltages, write/erase times, and the initial charge state of the floating poly-Si gate and compared, to a simple physical model for a variety of different device structures. This model depends on the interface limited (Si-rich-SiO2-SiO2interfaces) enhanced current injection observed for the dual-electron-injector stacks at moderate gate voltages for both voltage polarities, the changing electric fields in the SiO2layers as the floating polycrystalline silicon gate electrode is charged or discharged, and the voltage-dependent capacitance of the dual-electron-injector stack. Good agreement is observed between the experimental data and this model. This model will be the starting point in designing more complicated device arrays for nonvolatile memory applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Achieving accuracy in transistor and thyristor modeling

    Page(s): 1053 - 1059
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    There has been a great deal of progress both in the area of device modeling and in quantifying many of the physical Phenomena operating in silicon. However, there are questions concerning the consistency of the various models and there are uncertainties regarding the formulations af many of the important physical phenomena. In this paper the consistency between the present "exact" theory and three other models will be examined in the context of analyzing a diode, transistor, and thyristor. In addition, the available experimental and theoretical data on band gap narrowing (BGN) will be studied including recent data from an electron beam probing experiment (EBIC). The latter allows a model for BGN to be formulated based solely on experimental data ar concentrations up to 1020cm-3. New data will also be presented which establish a basis for the dependency of Shockley-Read-Hall (SRH) lifetime on impurity concentrations as well as showing that Auger recombination may operate through defect centers rather than being band to band. The literature will be reviewed and formulations for carrier degeneracy, impurity deionization, carrier-carrier scattering, and the temperature dependence of the carrier mobilities will also be studied. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An improvement of the interface properties of plasma anodized SiO2/Si system for the fabrication of MOSFET's

    Page(s): 1060 - 1065
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    A new annealing process in chlorine ambient produced by passing argon through a CCl4container for reducing the interface states of the plasma anodized SiO2/Si system was developed. At optimum annealing conditions, the interface state density was reduced to about 1010states/eV . cm2. Application of the oxide to the fabrication of MOSFET's shows that the devices obtained have lower threshold voltage and higher mobility than those fabricated with thermal oxidation in dry oxygen. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Buried channel GaAs MESFET's—Scattering parameter and linearity dependence on the channel doping profile

    Page(s): 1065 - 1070
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    The influence of the epitaxial structure (doping profile) in the channel region of a GaAs MESFET on its small signal scattering parameters is investigated both theoretically and experimentally. The large signal frequency behavior of FET's with a buried channel is compared with that of uniformally doped FET's. In the case of buried channel devices a much smaller variation of the s parameters with frequency is observed. This phenomenon can be understood by considering the inner transistor to consist of a two-dimensional transmission line. The principle of this new model, which is mainly based on technological data, is presented. Furthermore, the improvement of the nonlinear distortion is investigated. The FET's with a graded doping profile show very small intermodulation products, -42 dBm for an input power level of 4 dBm (Pout= 9 dBm: 1-dB gain compression) at a relatively small drain-source voltage of only 4 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The implanted zener diode (IZD) as an input protection device for MOS integrated circuits

    Page(s): 1071 - 1077
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB)  

    Phosphorus implantation, performed prior to the major standard process steps in p-channel technology, is used for a well controllable reduction of the breakdown voltage of planar diodes down to values which makes them suited as protection devices. In these devices the walk-out of the breakdown voltage, which is characteristic for the field-plated types of protective devices is almost completely eliminated. The dynamic resistance of the implanted diodes can be considerably reduced by providing a second p+diffusion which gives rise to parasitic bipolar transistor operation during breakdown. The dynamic resistance is found to be linearly dependent on the width of the space charge layer which is ascribed to microplasma phenomena occuring during breakdown. The overvoltages against which the new devices can offer protection when used in a distributed resistance configuration of 200-µm width, are shown to be in the 10-60-kV range. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A two-phase shift register using Si tunnel MIS switching diodes

    Page(s): 1078 - 1083
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    A novel monolithic shift register consisting of tunnel MIS switching diode arrays is proposed, in which gold and molybdenum electrodes overlapping in part are arranged in close vicinity on thin oxides formed on an n on p+silicon epitaxial wafer. Directional shift with two-phase clocks is achieved by making use of unsymmetric electrode configurations and current coupling effects between adjacent elements together with the difference in the sustain voltages of ON states between the two metals. Both ten and twenty-bit devices have functioned as designed. The margins in the driving conditions depend on the unsymmetry in the electrodes. The maximum operation frequency of 3 MHz has been attained which is limited by the CR time constant. The proposed register can be realized with very simple fabrication processes which involve no impurity diffusion. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

    Page(s): 1084 - 1087
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 1010cm-2. The effective carrier mobility calculated from the drain conductance is 750 cm2/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electron beam direct writing technology applied to 512 kbit ROM with 1 µm geometry

    Page(s): 1088 - 1094
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2144 KB)  

    A 512 kbit read-only memory (ROM) to store Chinese ideographs has been fabricated using variable-shaped electron beam and dry-etching lithography. 1.0-µm minimum line width was used to delineate device area spacings smaller than those obtained with conventional design rules using photoimaging techniques. SiO2, Si3N4, and polysilicon etchings were accomplished by reactive sputter techniques with CF4+ H2and CCl3F gases using negative electron beam resist PGMA and positive resist AZ-2400. Al etching was carried out by plasma with CCl4gas using negative electron beam resist NER-1. The alignment marks detectability and their locating accuracy were improved by properly using the basis arithmetic operations, subtraction and summation, in backscatter signal processings. 6.6 mm × 8.9 mm chip-by-chip alignment yielded about 0.2-µm level-to-level registration accuracy. Memory cell size and chip size are 5.2 µm × 8.4 µm and 6.6 mm × 8.9 mm, respectively; access time and power dissipation are 400 ns and 800 mW, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimum basewidth of limiter diode for maximum power handling capability

    Page(s): 1095 - 1096
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    In a microwave multidiode limiter most of the line current flows through the input diode at high power. No design guideline exists in the literature for choosing optimum basewidth of the diode for high power handling capability. This paper gives design procedure for calculation of optimum basewidth for maximum power handling and shows that power handling capability increases with the increase in basewidth till a certain limit and then decreases for any further increase in basewidth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • GaAs MIS solar cells with evaporated tin oxide interfacial layers

    Page(s): 1097 - 1098
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    GaAs metal-insulator-semiconductor (MIS) solar cells with vacuum-deposited tin oxide interfacial layers have been investigated. Open-circuit voltages of 0.765 V were observed, 62 percent higher than those of cells made without the tin oxide layer. The dependence of open-circuit voltage on interfacial layer thickness indicated a peak at 20-Å width. The results suggest that VOCcould be further improved by reduction of pinhole area in the interfacial layer. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparison of various source-gate geometries for power MOSFET's

    Page(s): 1098 - 1101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A simplified model is used to compare the influence of layout geometry on the parasitic drain resistance of a vertical DMOSFET. For each case, optimum dimensions are determined. For every geometry considered at least one-half of the total area is available for current conduction. The hexagon has been favored by some workers but slightly better results can be achieved with rectangles or with circles on hexagonal centers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

    Page(s): 1101 - 1103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    In relatively heavily and deeply boron-implanted n-channel MOSFET's, we found the anomalous phenomenon that the threshold voltage increases with decreasing channel length over a wide range of channel lengths. This is quite contrary to the well-known short-channel effect associated with the dependence of the threshold voltage on the channel length. It is difficult to explain this phenomenon directly by any simplified models that have been presented to date. In this brief, we present mainly the detailed experimental results of such an anomalous short-channel effect. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Charge hysteresis measurements of MOS structures

    Page(s): 1103 - 1105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    A method for charge hysteresis investigation in MOS structures is presented, which is based on direct charge measurement using constant current source and time readout. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Back cover]

    Page(s): c4
    Save to Project icon | Request Permissions | PDF file iconPDF (2476 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology