By Topic

Electron Devices, IEEE Transactions on

Issue 2 • Date Feb. 1980

Filter Results

Displaying Results 1 - 25 of 31
  • [Front cover and table of contents]

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (266 KB)  
    Freely Available from IEEE
  • Introduction

    Page(s): 321
    Save to Project icon | Request Permissions | PDF file iconPDF (192 KB)  
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power DMOS for high-frequency and switching applications

    Page(s): 322 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1088 KB)  

    The virtues of DMOS over other MOS technologies are first presented. The design considerations for the device are then given. Device fabrication and characteristics are also shown. With the data from these devices, a small-signal low-frequency model is derived which incorporates velocity saturation. The high-voltage breakdown is considered and an analysis of both the theoretical and experimental values are compared. Both punchthrough and avalanche breakdown of the DMOS device are discussed. The device has exceptional power gains in the VHF region considering its simplicity in design rules. A high-frequency linear model is constructed and is valid up to several gigahertz. Several improvements are proposed involving more strigent design rules which should yield power gains in the gigahertz region. With the process presented in this paper both high-frequency performance and high-voltage breakdown are obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power MOSFET's for medium-wave and short-wave transmitters

    Page(s): 330 - 334
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    This paper describes design and performance of a high-frequency power MOST used for switching-mode power amplifiers in the medium-wave (500 kHz to 1.5 MHz) or short-wave (1.5 MHz to 30 MHz) transmitters whose output power is in the vicinity of 1 kW. To obtain the drain-source voltages greater than 200 V with on-resistance remaining approximately 1 Ω, the offset gate length and field plate length of the high-frequency power MOST are optimized as well as offset gate layer concentration. Employing the molybdenum gate fabricated by RF diode sputter, the MOST operates at high speed with turn-on and turn-off times of 22 and 25 ns, respectively. A high-temperature operation test was performed to assure the stability and reliability of the device. The test results indicate that phosphosilicate glass polarization affects the device reliability only when offset gate layer concentration is much lower than the optimized value. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A complementary pair of planar-power MOSFET's

    Page(s): 334 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A complementary pair of planar-power MOSFETs has been developed, each of which has drain breakdown voltage as high as 250 V and 12-A current capability. These devices have field plates on the ion-implanted gate offset region to realize high-breakdown voltages and large current capabilities. The field distribution behavior of a field-plated high-voltage MOSFET and a non-field-plated device are compared. In this procedure, the first-order theory of pinchoff voltage of the offset region, the most important parameter for a planar-power MOSFET, is derived for high-voltage and high-current capability design. Experimental results to support the usefulness of a field plate for improving breakdown voltage and current capabilities are obtained and discussed. Finally, future possible developments of these devices, such as high-voltage and high-current approaches, are described and a new type of device structure is proposed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-performance planar power MOSFET

    Page(s): 340 - 343
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    Design and experimental realization of a 450-V, 0.75-Ω DMOS power transistor are discussed. Optimization criteria are evaluated for the control of parasitic elements of the planar diffused design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 600-volt MOSFET designed for low on-resistance

    Page(s): 343 - 349
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB)  

    A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Epitaxial VVMOS power transistors

    Page(s): 349 - 355
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    The design aspects of a V-groove vertical-geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in this paper. The process has several features including ease of fabrication, good threshold voltage controllability, and high breakdown voltage. Expressions for the on-resistance as a function of device parameters and for the device capacitances as a function of the geometric features of the transistor are derived. Experimental results on fabricated devices are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors

    Page(s): 356 - 367
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1656 KB)  

    Power MOS transistors have recently begun to rival bipolar devices in power-handling capability. This new capability has arisen primarily through the use of double-diffusion techniques to achieve short active channels and the incorporation of a lightly doped drift region between the channel and the drain contact, which largely supports the applied voltage. Many different structures have been proposed to implement these new devices. This paper considers three of the most common-LDMOS, VDMOS, and VMOS. Structural differences which result in on-resistance and transconductance differences between the devices are described. Quantitative models, suitable for device design, are developed for the on-resistance of each type of structure. These models are developed directly from the physical structure (geometry and doping profiles) so that they are useful in optimizing a particular device structure or in quantitatively comparing structures for a particular application. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A power junction gate field-effect transistor structure with high blocking gain

    Page(s): 368 - 373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new bipolar transistor—GAT

    Page(s): 373 - 379
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    A new bipolar transistor named Gate Associated Transistor (GAT) was proposed and the operating mechanisms were verified. The structure of the GAT has a unique base region consisting of an FET merged into the base of a standard bipolar transistor. The operating mechanisms and characteristics of the GAT were investigated and compared with those of standard power transistors. The most outstanding feature of the GAT was a large area for safe operation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Insulated-gate planar thyristors: I—Structure and basic operation

    Page(s): 380 - 387
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    A high-voltage planar triac which is controlled by an insulated-gate terminal is described. Its structure is related to the DMOS transistor on which it is based and its multiple operating modes are discussed in terms of an equivalent circuit composed of MOS and bi-polar transistors and resistors. A typical junction-isolated device has a 150-V breakdown and an on-resistance less than 10 Ω for a 400-µm-wide channel. The on-resistance can easily be scaled to very low values simply by increasing the device width. Extension of the MOS thryistor concept to other devices and higher voltages is described. Quantitative analysis and modeling of these new devices are described in a companion paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Insulated-gate planar thyristors: II—Quantitative modeling

    Page(s): 387 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    The basic modes of operation of a new planar, high-voltage thyristor which is controlled by an insulated gate are described in Part I. This paper presents models for the dc operation of the device. Low-current nonregenerative operation is described by an equivalent circuit containing MOSFET's, bipolar transistors, and resistors. These are analyzed by a general-purpose nonlinear circuit analysis program. Sophisticated transistor models, both bipolar and MOS, are required to accurately represent the component devices, and their characteristics are discussed. The high-conductivity state is modeled as a one-dimensional p-i-n diode. Determination of appropriate parameters is described and simulations are compared to measured characteristics. The resulting models are suitable for the design of devices with a wide variety of dc characteristics. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal stability and secondary breakdown in planar power MOSFET's

    Page(s): 395 - 398
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p-on p+epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computer analysis of breakdown mechanism in planar power MOSFET's

    Page(s): 399 - 400
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    Breakdown mechanism in planar power MOSFET's having high breakdown voltage is investigated. Precise electric field distribution is obtained by two-dimensional numerical analysis. This field distribution is used to optimize device structure and to predict breakdown voltage. A technique for reducing the electric field on the silicon surface by equalizing its distribution is presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The low light level potential of a CCD imaging array

    Page(s): 401 - 405
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    Some limitations to the operation of a CCD TV camera sensor at low light levels are discussed. Transfer inefficiency with small charge packets is analyzed theoretically, and the prediction made that with good processing this should not be a serious problem. The principal limitation is seen to be the output amplifier, and a new low-noise output detector, the "floating surface detector," is described in detail. At -50°C it yields a noise equivalent signal of 16 electrons and a dynamic range of 85 dB over a 1-MHz video bandwidth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling and experimental simulation of the low-frequency transfer inefficiency in bucket-brigade devices

    Page(s): 405 - 414
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB)  

    The work presented in this paper extends the available theory and it also presents a model for the low-frequency charge transfer in MOS bucket-brigade devices (BBD's). Our new theory which characterizes the low-frequency component of transfer inefficiency in terms of the subthreshold current is frequency independent and it incorporates both channel-length and barrier-height modulations. This model was verified experimentally on simulated BBD's. After proving both theoretically and experimentally that the low-frequency transfer inefficiency of BBD devices is due to subthreshold current, we successfully used this knowledge to design an improved BBD device. This improved device includes only one extra ion-implantation step relative to the original BBD device. An ion implant is used in part of the BBD channel. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analysis and the fabrication technology of the lambda bipolar transistor

    Page(s): 414 - 419
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    A new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, which is called the Lambda bipolar transistor, is studied both experimentally and theoretically. The principal operation of the Lambda bipolar transistor is characterized by the simple circuit model and device physics. The important device properties such as the peak voltage, the peak current, the valley voltage, and the negative differential resistance, are derived in terms of the known device parameters. Comparisons between the characteristics of the fabricated devices and the theoretical model are made, which show that the analysis is in good agreement with the observed device characteristics. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ion-implanted low-barrier PtSi Schottky-barrier diodes

    Page(s): 420 - 425
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    An ion-implanted, shallow n+layer has been used for lowering the barrier height of PtSi-n-Si Schottky diodes. Barrier height reductions up to 200 mV have been achieved with little degradation of the diode's reverse-current characteristics. During silicide formation, the implanted ions are "pushed" ahead of the PtSi-Si reaction zone and pile up at the silicide-silicon interface, resulting in more barrier lowering than would be expected from the ion-implant dose. A model including the impurity pileup is presented and calculations based on the model are shown to be in reasonable agreement with experimental measurements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optically induced AM and FM in IMPATT diode oscillators

    Page(s): 426 - 432
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    Optical modulation of an IMPATT oscillator is investigated both theoretically and experimentally. Detailed computer simulations of the oscillatory dynamics are used to determine the basic mechanisms responsible for optical modulation and to examine the extent of and means for optimizing the optical response. It is shown that optically induced changes in the conduction current minimum and in the levels of carrier slowdown or depletion-region modulation are the primary mechanisms responsible for optical modulation. Amplitude modulation via an optical quenching of the oscillations is found to be the dominant response, although optical enhancement is also possible under certain conditions. It is demonstrated that substantial levels of FM can also be produced, despite the fact that the IMPATT susceptance is insensitive to illumination. The experimental results are found to be in general agreement with the predictions of the theory. It is concluded that the optical response of the IMPATT is sufficient to make optical modulation a useful technique. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transient temperature behavior in pulsed double-drift IMPATT diodes

    Page(s): 433 - 442
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    The temperatures in a pulsed double-drift IMPATT diode are calculated as a function of position and time by a finite difference calculation using the alternating direction algorithm. The results are given as a function of pulse length and duty factor for a typical double-drift diode designed to operate near X band. Techniques are described for choosing spatial meshes and time integrals which vary with position and time in a way that minimizes computation time. Numerical results are chosen to illustrate the distribution of temperature within the diode at different times during the pulse, the effect of a temperature-dependent breakdown voltage upon radial temperature distribution, and the interplay between the short thermal-diffusion times within the GaAs diode and the long times associated with the slow heating-up of the heat sink at great distances. An extended definition of thermal resistance for pulsed diodes is introduced and the implications upon reliability are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An X-band SOS resistive gate—insulator—semiconductor (RIS) switch

    Page(s): 442 - 448
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    The new X-Band Resistive Gate-Insulator-Semiconductor (RIS) switch has been fabricated on silicon-on-sapphire, and its equivalent circuit model characterized. An RIS SPST switch with 20-dB ON/OFF isolation, 1.2-dB insertion loss, and power-handling capacity in excess of 20-W peak has been achieved at X band. The device switching time is on the order of 600 ns, and it requires negligible control holding current in both ON and OFF states. The device is compatible with monolithic integrated-circuit technology and thus is suitable for integration into low-cost monolithic phase shifters or other microwave integrated circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application of anodization in Oxygen plasma to fabrication of GaAs IGFET's

    Page(s): 449 - 455
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Anodic oxide grown in oxygen plasma has been used to fabricate the gate insulator of GaAs insulated-gate field-effect transistors (IGFET's), by patterning the gate electrode of 1.2 µm in length with the dry etching process. It is found that the oxidation process does not damage the electrical property of the channel layer. However, the trap states at the interface between the oxide and the channel affect the low-frequency characteristics, especially at positive gate voltage. The IGFET's show a good high-frequency performance comparable to GaAs MESFET's. The following characteristics are confirmed from the measurement of the S-parameters and the equivalent circuit analysis; the maximum stable power gain is 11.4 dB at 8 GHz, the cut-off frequency of the unilateral power gain is 48 GHz, and the intrinsic gain-bandwidth product is 18 GHz. The minimum noise figure is measured to be 4.8 dB at 8 GHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • I—V characteristics of GaAs MESFET with nonuniform doping profile

    Page(s): 455 - 461
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    A simple analytical model of a GaAs MESFET with non-uniform doping is proposed. The analysis shows that at gate voltages well above the threshold (0.2-0.4 V) for a typical device the current saturation is related to the velocity saturation (with a possibility of a stationary domain formation at drain-to-source voltages high enough). Closer to the threshold the saturation is due to the channel pinchoff. In both regimes the nonuniformity of the doping profile may be essential. Another factor taken into consideration is the source series resistance which includes the contact resistance and the resistance of the gate-to-source region of the device. The calculated dependences of the transconductance and drain current on the gate voltage are in good agreement with the experimental results obtained by Eden, Zucca, Long, and others [1]. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Determination of capture cross section and surface-states concentration profile using the surface-acoustic-wave convolver

    Page(s): 461 - 466
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    Energy distribution of surface states and majority-carriers capture cross section is determined using the surface-acoustic-wave (SAW) convolver. The semiconductor is placed a small distance above the SAW delay line, with a uniform air gap between the two media. A fast rise time dc pulse is applied across the semiconductor-delay line structure, and the resulting change in the SAW propagation loss is observed. The transient response of the SAW propagation loss represents the emission or trapping of majority carriers from surface states. From this transient response, the capture cross section and the concentration profile of the surface states are determined. The results obtained agree with the already known distribution of fast surface states; it is constant at the middle of the gap and increases towards the conduction band, whereas the capture cross section is constant in the middle of the gap and decreases toward the conduction band. This new SAW technique is simple, sensitive, and requires no contact to the semiconductor surface. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology