IEEE Transactions on Computers

Issue 11 • Nov 1991

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Displaying Results 1 - 18 of 18
  • On evaluating the cumulative performance distribution of fault-tolerant computer systems

    Publication Year: 1991, Page(s):1301 - 1307
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Fault-tolerant computer systems may be evaluated by calculating their cumulative performance (e.g., number of processes jobs) over a finite mission time. A method for calculating the cumulative performance distribution assuming that the system fault-repair behavior can be modeled by a homogeneous Markov process is described. The method proposed for calculating the probability distribution of the a... View full abstract»

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  • An efficient method of computing generalized Reed-Muller expansions from binary decision diagram

    Publication Year: 1991, Page(s):1298 - 1301
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    An efficient method for the generation of all the 2n sets of generalized Reed-Muller (GRM) coefficients for a Boolean function f(X) of n variables using the binary decision diagram (BDD) is presented. The author describes the generation of RM coefficients from minterm values and relates them to the associated subfunctions. Examples are included to illustrate t... View full abstract»

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  • An efficient routing algorithm for realizing linear permutations on pt-shuffle-exchange networks

    Publication Year: 1991, Page(s):1292 - 1298
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    The authors present an efficient routing algorithm for realizing any permutation in LIN (linear-permutation-class) on single-stage shuffle-exchange networks with k×k switching elements, where k=p is a prime number. For any positive integer number n there are N=kn processors connected by the network. The proposed algorithm can r... View full abstract»

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  • An algorithm for the computation of binary logarithms

    Publication Year: 1991, Page(s):1267 - 1270
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    The author presents a simple algorithm for the computation of the base-2 logarithm of a given binary number. The concept can be easily extended to base-N. Unlike other methods, this is not a curve fitting of the base-2 logarithm of a given binary number. The algorithm constitutes a simple step-by-step, bit-by-bit, computation of the logarithm of binary numbers. It can be easily implemente... View full abstract»

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  • Using horizontal prefetching to circumvent the jump problem

    Publication Year: 1991, Page(s):1287 - 1291
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    The principle of a novel prefetching mechanism, horizontal demand prefetching, is presented. The mechanism allows deep prefetching without jump related misses by prefetching horizontally across independent instruction streams. The scheme can achieve high memory utilization at the expense of processor utilization. The mechanism permits very rapid context switching with no overhead for a hardware-li... View full abstract»

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  • Pipeline design tradeoffs in a 32-bit gallium arsenide microprocessor

    Publication Year: 1991, Page(s):1214 - 1224
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    The results of a study of the instruction pipeline design for a 32-b single-chip GaAs microprocessor are presented. The authors introduce nine candidate solutions for the instruction pipeline, define a set of technology-dependent and application-related parameters, and present the results of the comparative performance evaluation. Important differences between GaAs and silicon, which are relevant ... View full abstract»

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  • The run-time efficiency of parallel asynchronous algorithms

    Publication Year: 1991, Page(s):1260 - 1266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    The problem studied is similar to the problems found in multiprocessor operating systems. The lockout problem in multiprocessor operating systems is a direct result of multiple processors attempting to process common data structures asynchronously. There are numerous such shared data structures. The models developed are applicable to the study of contention for software and hardware resources in m... View full abstract»

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  • A comparison-based approach to multicomputer system diagnosis in hybrid fault situations

    Publication Year: 1991, Page(s):1283 - 1287
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A comparison-based system-level fault diagnosis model is considered. Provided the number of faulty units and the number of incorrect outcomes (in the sense that a fault-free unit evaluates a faulty one to be fault-free) do not exceed given bounds, the necessary and sufficient conditions for the comparison assignment to achieve correct and complete diagnosis are determined. An O(n... View full abstract»

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  • Polynomial complexity algorithms for increasing the testability of digital circuits by testing-module insertion

    Publication Year: 1991, Page(s):1198 - 1213
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    The authors present a method for increasing the testability of combinational circuits for single stuck-at faults by partitioning the circuit and inserting testing-modules. A testing-module structure that allows lines in the circuit to be logically disconnected is shown. It allows the circuit to be partitioned into independent subcircuits. A test generation algorithm that is based on test set mergi... View full abstract»

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  • Efficient unidirectional error codes for block memories

    Publication Year: 1991, Page(s):1257 - 1259
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Unidirectional error-correcting (UEC) codes are presented that are suitable for memory systems in which data are stored in blocks consisting of tracks. UEC codes are proposed that can correct any error pattern consisting of unidirectional errors confined to a single track. For two or more information tracks, a code exists for any given nontrivial length. It is shown that the codes can be construct... View full abstract»

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  • A variation on the hypercube with lower diameter

    Publication Year: 1991, Page(s):1312 - 1316
    Cited by:  Papers (168)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    A new interconnection structure is proposed as a basis for distributed-memory parallel computer architectures. The network is a variation of the hypercube and preserves many of its desirable properties, including regularity and large vertex connectivity. It has the same node and link complexity, but has a diameter only about half of the hypercube's. Some of the basic properties of this topology ar... View full abstract»

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  • Indirect star-type networks for large multiprocessor systems

    Publication Year: 1991, Page(s):1277 - 1282
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors propose three indirect star-type networks, the indirect star networks I and II and the star-delta network, and investigate their properties. An indirect star-type network is obtained by unfolding the star graph. The star-delta network is obtained through an unfolding scheme based on the recursive property of the star graph, and has n-1 switching stages. The star-delta network ... View full abstract»

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  • Hard-wired multipliers with encoded partial products

    Publication Year: 1991, Page(s):1181 - 1197
    Cited by:  Papers (22)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB)

    A multibit overlapped scanning multiplication algorithm for sign-magnitude and two's complement hard-wired multipliers is presented. The theorems necessary to construct the multiplication matrix for sign-magnitude representations are emphasized. Consequently, the algorithm for sign-magnitude multiplication and its variation to include two's complement numbers are presented. The proposed algorithm ... View full abstract»

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  • Self-diagnosis of failures in VLSI tree array processors

    Publication Year: 1991, Page(s):1252 - 1257
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The authors present a built-in self-test and diagnosis scheme for detecting and locating the faulty cells in a tree array. Since the signatures of all cells are generated simultaneously (i.e., parallel testing), the time required for the signature generating stage is constant, independent of the array size. Each cell (processing element) generates pseudorandom test patterns and compresses test res... View full abstract»

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  • Topological via minimization revisited

    Publication Year: 1991, Page(s):1307 - 1312
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The topological via minimization problem in a two-layer environment is considered. A set of n two-terminal nets in a bounded region is given. The authors attempt to find a homotopy to assign nets to distinct layers so that no two nets on the same layer cross each other and the number of vias is minimized. A recursive approach in which an optimal solution to a two-sided channel routing pro... View full abstract»

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  • Undirected graph models for system-level fault diagnosis

    Publication Year: 1991, Page(s):1271 - 1276
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The author considers two comparison-based diagnosis models previously introduced by K.Y. Chwa et al. (1981) and M. Malek (1980). For each of them, classical t-diagnosability and probabilistic diagnosability based on the maximum likelihood principle are discussed, probabilistic model for comparison testing is introduced. In all considered models, optimal diagnosable systems, i.e., those wh... View full abstract»

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  • Compile-time scheduling and assignment of data-flow program graphs with data-dependent iteration

    Publication Year: 1991, Page(s):1225 - 1238
    Cited by:  Papers (26)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1268 KB)

    Four scheduling strategies for dataflow graphs onto parallel processors are classified: (1) fully dynamic, (2) static-assignment, (3) self-timed, and (4) fully static. Scheduling techniques valid for strategies (2), (3), and (4) are proposed. The focus is on dataflow graphs representing data-dependent iteration. A known probability mass function for the number of cycles in the data-dependent itera... View full abstract»

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  • Performability analysis of distributed real-time systems

    Publication Year: 1991, Page(s):1239 - 1251
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    An algorithm and a methodology for the performability analysis of repairable distributed real-time systems are presented. The planning cycle of a real-time distributed system, which normally consists of several task invocations, is first identified. The performability distribution at the end of the planning cycle is determined by repeated convolutions of performability densities between task invoc... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org