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IEEE Transactions on Electron Devices

Issue 8 • Aug. 1978

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Displaying Results 1 - 25 of 40
  • [Front cover and table of contents]

    Publication Year: 1978, Page(s): c1
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    Freely Available from IEEE
  • Foreword SOS special issue—SOS technology

    Publication Year: 1978, Page(s):857 - 858
    Cited by:  Papers (3)
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  • SOS wafers—Some comparisons to silicon wafers

    Publication Year: 1978, Page(s):859 - 863
    Cited by:  Papers (3)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Some comparisons between SOS wafers and silicon wafers used in the processing of MOS integrated circuits are presented. These comparisons are useful in understanding the differences in handling techniques, specifications, and costs; as well as identifying areas of future material quality improvement and cost reduction programs. Growth conditions, material quality, geometric dimensions, epitaxial-f... View full abstract»

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  • The flame fusion technique: Present state of the art at the material, device, and circuit levels

    Publication Year: 1978, Page(s):864 - 868
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    One of the present limitations of silicon-on-sapphire (SOS) technology is the cost of the starting material. It has been proved that this technology allows to build circuits with higher operating frequencies and denser than bulk technology. These advantages would be increased thanks to a lowering of substrate cost. One of the solutions is to use the flame fusion (FF) technique to replace Czochrals... View full abstract»

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  • Fabrication and properties of ESFI-SOS-MOST's suitable for both low-voltage and low-power circuits

    Publication Year: 1978, Page(s):868 - 873
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    The fabrication and the properties of ESFI-SOS p-channel deep-depletion and n-channel inversion transistors are discussed. These devices are aimed to be used in integrated circuits with both low supply voltage and low power consumption. It turns out that certain device parameters such as reverse current, leakage current, threshold voltage, and channel mobility are strongly correlated and that a pr... View full abstract»

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  • The use of a silicon-gate C-MOS/SOS test vehicle to evaluate technology maturity

    Publication Year: 1978, Page(s):873 - 878
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB)

    This paper describes a comprehensive test vehicle that has been used to characterize the silicon-gate C-MOS/SOS technology. Specifically, it has facilitated the verification of a set of topological layout rules and mask sequence which are producible industry-wide; the establishment of electrical design parameters; and has provided information on the present yield and performance range of the techn... View full abstract»

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  • C-MOS/SIS—Using selective SF6etching of {1102} sapphire

    Publication Year: 1978, Page(s):878 - 884
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    A process for selectively etching holes in {1102} sapphire using SF6in H2is described. SiO2, Si3N4, and combinations thereof are studied as possible etchant masks. Refilling the holes with epitaxial silicon produces an SIS (silicon-in-sapphire) wafer wherein the silicon islands are imbedded into the sapphire substrate. The electrical character... View full abstract»

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  • The subthreshold behavior of SOS MOST's

    Publication Year: 1978, Page(s):885 - 889
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    MOST subthreshold behavior is of importance in many modern dynamic and very-low-power circuits. SOS MOST's exhibit quite generally a lower transconductance than bulk Si MOST's. Comparison between SOS and bulk Si MOST's is made on the basis of a simple model in the weak inversion region. Experiments with n-and p-channel SOS MOST's fabricated with epi Si layer thicknesses ranging from 0.1 to 3 µ... View full abstract»

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  • Threshold voltage model of ESFI-SOS-MOS transistors

    Publication Year: 1978, Page(s):890 - 894
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A threshold voltage model for ESFI-SOS transistors is presented accounting for the thin-film structure and the existence of the silicon-sapphire interface. The model uses simplifying assumptions in order to obtain analytical expressions. In most practical cases the charge at the silicon-sapphire interface is sufficiently high to accomplish a saturation effect of the value of the threshold voltage.... View full abstract»

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  • Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

    Publication Year: 1978, Page(s):894 - 898
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" fo... View full abstract»

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  • Modeling the operation of the n-channel deep-depletion SOS/MOSFET

    Publication Year: 1978, Page(s):899 - 907
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    We present a model for the n-channel deep-depletion SOS/MOSFET which is valid over its entire operating range. This model, which is suitable for incorporation in a circuit simulation program, accurately predicts the source-to-drain current for device operation in depletion and in both weak and strong accumulation. Important aspects of the theory are 1) incorporation of the effect of the depth depe... View full abstract»

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  • The effect of a floating substrate on the operation of silicon-on-sapphire transistors

    Publication Year: 1978, Page(s):907 - 912
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    It was observed that during operation of SOS counter circuits, the propagation delay between stages was a function of the operating frequency. Further analysis proved the change in propagation delay to be associated with the change in the magnitude of a transient drain current. The origin of the transient current was found to lie in properties of the floating substrate. This paper discusses these ... View full abstract»

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  • Electron mobility in SOS films

    Publication Year: 1978, Page(s):913 - 916
    Cited by:  Papers (6)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Mobility of electrons in various thickness thin silicon films grown on two different high-temperature pre-epitaxial growth annealed sapphire substrates was measured as a function of the depth from the Si-SiO2 interface and the gate bias voltage at-50 to 120°C temperature range. The mobility is larger for electrons in thicker SOS films and in those films grown on higher temperature pre-epitaxi... View full abstract»

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  • C-MOS/SOS gate-protection networks

    Publication Year: 1978, Page(s):917 - 925
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1296 KB)

    To protect C-MOS/SOS LSI circuits from electrostatic discharge and resulting dielectric breakdown of the gate insulator, various gate-protection networks are employed. This paper reports on the evaluation of high-voltage diodes, Zener diodes, distributed diode-resistor combinations, and spark-gap devices for use in gate protection network applications. Results of pulse-power burnout, current-volta... View full abstract»

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  • An improved input protection circuit for C-MOS/SOS arrays

    Publication Year: 1978, Page(s):926 - 932
    Cited by:  Papers (11)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    A protective network for silicon-gate C-MOS/SOS arrays has been designed that is capable of protecting input circuits from static discharges in excess of 2200 V. This paper describes the results of a program undertaken at RCA to develop a protection network for C-MOS arrays on sapphire substrates capable of withstanding 1500-v static discharges. A test chip with eight input protection configuratio... View full abstract»

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  • C-MOS/SOS LSI input/Output protection networks

    Publication Year: 1978, Page(s):933 - 938
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    An improved input and output electrical surge protection has been developed for C-MOS and MNOS large-scale integrated circuitry fabricated on sapphire. The failure mode was designed to be the input- or output-series limiting diffused resistor, which can be controlled reliably through the fabrication processes. Forward-bias diodes attenuate the overvoltage surges. Failure energies and voltages have... View full abstract»

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  • The IC yield problem: A tentative analysis for MOS/SOS circuits

    Publication Year: 1978, Page(s):939 - 944
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1592 KB)

    Yield on integrated circuits is the result of the contribution of many parameters including number of masking steps, design dimensions, and intrinsic process steps. Test vehicles specific to each process to be investigated are used and through ring oscillators yield figures, and test pattern results, evaluation of yield, as well as identification of main causes of yield loss can be made. The test ... View full abstract»

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  • 4-µm LSI on SOS using coplanar-II process

    Publication Year: 1978, Page(s):945 - 951
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (921 KB)

    SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the ... View full abstract»

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  • 40-MHz CMOS-on-sapphire microprocessor

    Publication Year: 1978, Page(s):952 - 959
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1368 KB)

    Silicon-on-sapphire (SOS) technology has been applied to the RCA COSMAC microprocessor to obtain a high-speed single-chip CPU. The chip has 4827 transistors and measures 5.3 mm square. The low device count is obtained through use of bit-serial arithmetic logic, a byte-serial incrementer, and a 5-transistor static storage cell. The low parasitic capacitance of the SOS structure permits a 40-MHz clo... View full abstract»

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  • SOS Device radiation effects and hardening

    Publication Year: 1978, Page(s):959 - 970
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB)

    The status of radiation-hardening problems common to both C-MOS/SOS and C-MOS/Bulk and the role that the silicon-on-sapphire technology plays as a "dielectric isolation hardening process" fis briefly presented, The new radiation effects problems that are a result of implementing C-MOS technology in SOS instead of in bulk silicon are delineated and put into perspective The main emphasis is on back-... View full abstract»

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  • Island-edge effects in C-MOS/SOS transistors

    Publication Year: 1978, Page(s):971 - 978
    Cited by:  Papers (12)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1232 KB)

    The physical and electrical properties of C-MOS/SOS silicon island edges are investigated. Roughness of etched surfaces, nonuniform crystalline quality, and doping concentration along island-edge surfaces, and the formation of "V"-shaped grooves after thermal oxidation of silicon islands are related to leakage currents and other undesirable electrical characteristics. The interaction of oxide char... View full abstract»

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  • The effect of process variations on interfacial and radiation-induced charge in silicon-on-sapphire capacitors

    Publication Year: 1978, Page(s):978 - 982
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (691 KB)

    We have used extended-range MISC(V)measurement to carry out a preliminary study of the effect of the variation of epitaxial Si growth parameters on interfactial charge in ion implantation doped silicon-on-sapphire (SOS) capacitors. Our results to date show that 1) both the magnitude and the ploarity of the interfacial charge are affected by the Si growth rate; 2) the magnitude charge ar... View full abstract»

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  • Transient and total dose radiation characteristics of an SOS LSI array

    Publication Year: 1978, Page(s):982 - 988
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Transient and total dose characteristics of irradiated 300 gate LSI arrays are presented. These arrays are configured to carry out the arithmetic function of an Arithmetic-Logic Unit. Samples were fabricated with ion implanted source-drain regions, wet-or dry-oxide (SiO2) gate insulator, and n+deposited polysilicon gates. Irradiation sources were the AFCRL Linac operating wit... View full abstract»

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  • Short-channel C-MOS/SOS technology

    Publication Year: 1978, Page(s):989 - 995
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    Design, fabrication, and characterization of Si-gate short-channel C-MOS/SOS devices with channel length ranging from 1 to 3 µm are presented. Basic device parameters and their interrelations are discussed and illustrated in detail. Extremely-high-speed and low-power capability has been demonstrated for short-channel devices operating from a 5-V supply voltage. The process reproducibility and... View full abstract»

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  • A 2-µm silicon-gate C-MOS/SOS technology

    Publication Year: 1978, Page(s):996 - 1004
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    A 2-µm silicon gate deep-depletion C-MOS/SOS technology is described and characterized. The fabrication technology features all dry processing (ion milling and plasma etching) ion implanted source and drain, 2-µm features on all levels, phosphorous glass reflow for improved yield, and low-temperature processing (T ≤ 875°C). Characterization of the static electrical parameters ... View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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