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Electron Devices, IEEE Transactions on

Issue 4 • Date April 1978

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Displaying Results 1 - 21 of 21
  • [Front cover and table of contents]

    Page(s): c1
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  • Foreword

    Page(s): 401
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  • Fabrication of integrated injection logic with electron-beam lithography and ion implantation

    Page(s): 402 - 407
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    Integrated injection logic gates have been fabricated using electron-beam lithography and ion implantation. A factor of five reduction in gate area over conventional designs was achieved by using minimum linewidths of 1.25 µm. Average propagation delay of 6 ns at 100 µA/gate injector current and speed-power product of 0.13 pJ at 5 µA have been measured on five collector, stick geometry, n+guard ring device structures. The delay time is a factor of three and the speed-power product is a factor of five better than typical conventionally sized structures fabricated with photolithography. A minimum delay of 3.6 ns has been achieved on five collector device structures designed for maximum speed. View full abstract»

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  • The use of submicrometer electron-beam lithography for fabricating 4-kbit CCD memory arrays

    Page(s): 408 - 412
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    A 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features. The basic CCD cell size is 3.2 µm × 4.2 µm consisting of a storage area 2.4 µm × 3.6 µm with a 0.8-µm barrier and a 0.6-µm channel stop. To make these small CCD's, as well as the associated short-channel MOSFET's, we modified the conventional MOS wafer processing. The new process for two-level polysilicon gates requires six electron-beam levels with a minimum resist feature of 0.3 µm. Alignment of the electron-beam patterns uses Ta benchmarks which we found to be compatible with MOS devices. Testing of the 4-kbit array and other shift resisters showed submicrometer channel-stops and barriers are feasible while maintaining low channel-to-channel crosstalk and charge-transfer efficiency greater than 0.9995. In addition, low capacitance output circuits defined by electron-beam lithography can detect the small number of charges in the high-resolution CCD's and amplify the signal sufficiently to recirculate the data. View full abstract»

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  • Fabrication of a low-noise beam-leaded microwave bipolar transistor by electron- and photolithography

    Page(s): 413 - 419
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    A low-noise beam-leaded microwave bipolar transistor was fabricated with a combination of electron- and photolithography. Four of the eleven levels which were related to the patterning of the active region were patterned directly on the silicon wafers by the Bell Laboratories Electron Beam Exposure System (EBES). The registration tolerance of the 1-µm emitter stripes to the thin-gold metallization fingers was ± ¼-µm. This was routinely achieved on the 2-in wafers for all the levels written on EBES. The device processing employed a modified self-aligned emitter process which allows very highly doped inactive base and emitters without the problem of soft emitter-base junction. RF measurements of typical transistors show a minimum noise figure of 1.8 dB and an available gain of 12 dB at 1.7 GHz. View full abstract»

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  • A double-exposure technique to macroscopically control submicrometer linewidths in positive resist images

    Page(s): 419 - 424
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    A double-exposure, end-point detection technique (DEEP-DET) enables precise development of lines below 1 µm. A small test area first receives a precalibrated blanket exposure. During the masking operation, features of several micrometers are printed on it. When the resist in the test area, observed by eye or under a low-power microscope, is completely cleared, the water is accurately developed. An efficient method of precalibration is described. The capability of a 0.01-µm accuracy is estimated analytically. An experimental demonstration of the accuracy and a scheme for automatic detection are given. View full abstract»

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  • Performance characteristics of diazo-type photoresists under e-beam and optical exposure

    Page(s): 425 - 430
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    The performance characteristics of three different diazotype positive photoresists such as Shipley AZ2400, Kodak 809, and Polychrome PC129, are compared after optical exposure and electron-beam exposure. The development rates for both e-beam and optically exposed resists are measured by an in-situ automated technique using the IBM Film Thickness Analyzer. The optical exposure parameters are obtained at three wavelengths (4358, 4047, and 3650) by computer-controlled transmission measurements. The optical exposure and development parameters permit direct quantitative comparisons for these photoresists. The development rates of e-beam and optically exposed resists are compared. Also a comparison of e-beam sensitivity between the three resist systems is made by studying the resist profile shape after development in the scanning-electron microscope (SEM). View full abstract»

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  • High-resolution sampling SEM for quantitative investigations of semiconductor devices and integrated circuits

    Page(s): 431 - 434
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    A scanning microscope has been interfaced with sampling circuitry to record high-speed voltage waveforms at internal points in devices. The system is capable of resolving rise times of 100 ps and voltage steps with an uncertainty of less than 10 mV. Results demonstrate the operation of the 4-GHz sampling SEM. View full abstract»

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  • A simplified model for subpinchoff conduction in depletion-mode IGFET's

    Page(s): 435 - 441
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    An expression is developed for theI-Vcharacteristics of a depletion-mode device in the subpinchoff region. This expression is found to correlate well with experimental results taken on n-channel polysilicon gate devices, predicting a region of exponential current rise with gate voltage. It is of interest to note that the subpinchoffI-Vcharacteristics of a depletion-mode device form a dual to those of an enhancement-mode device. View full abstract»

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  • Analytical thermal response of a multiple-layer device under the semi-infinite approximation

    Page(s): 441 - 448
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    An analytical method for the analysis of the transient thermal response of a multiple-layer semi-infinite solid-state device is described. The method uses the Laplace transform to obtain solutions of the coupled partial differential equations. The solutions indicate the time limits for which thet^{1/2}dependance of the surface temperature is valid. The temperature distribution within the layers indicates that an exponential type distribution results. As an example, computations were carried out on the structure of a typical soft-soldered power transistor, using a digital computer. View full abstract»

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  • An analysis of the concave MOSFET

    Page(s): 448 - 456
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    The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed. View full abstract»

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  • Emission reserve mapping of CRT-type cathodes

    Page(s): 456 - 464
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    The "dip test" was recommended in 1956 to evaluate the emission activity of cathodes, and this method is now in common use for evaluation of cathodes in microwave tubes and in other electron devices wherein unvarying geometry and field configuration permit simple application of the test and interpretation of results. Application of the "dip test" to CRT cathodes, however, involves complexities associated with a) variation of emission current density from center to edge of the cathode, b) variation of the emitting area and current density with intensity modulation (grid voltage), and c) variation of the grid-cathode geometry which takes place during the cooling period of the dip test. A method has now been developed for accurately evaluating the cathode activity for varying radii of concentric circular cathode areas. A figure of merit is introduced which characterizes the cathode emission. View full abstract»

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  • Emitter current-crowding in high-voltage transistors

    Page(s): 465 - 471
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    The problem of emitter current-crowding is treated for the case where the base is heavily doped with respect to the collector and the transistor is operating in the quasisaturation region. Closed-form solutions for terminal currents and current gain are derived in terms of elliptic integrals and other related functions. Good agreement with experimental data is demonstrated and various design implications of the theory are discussed. View full abstract»

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  • Measurement of carrier lifetime profiles in diffused layers of semiconductors

    Page(s): 472 - 477
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    This paper describes a method for the measurement of carrier generation lifetime profiles within diffused layers in semiconductors. Knowledge of the lifetime distribution is the key to being able to accurately predict terminal electrical properties as well as understanding the physical processes operating in devices. In addition, the lifetime profile should be a sensitive measure of the quality of the device processing. Although many methods have been developed and applied to the measurement of lifetime in uniformly doped semiconductor regions, this is the first time that lifetime profile measurements have been achieved within diffused layers. In this paper, the lifetime measurements were done by the ZERBST technique using an MOS capacitor created by anodization of the wafer surface. The use of ZERBST plots allows the easy separation of surface recombination from the bulk lifetime eliminating one major source of error during lifetime measurements. In addition, the MOS capacitor used for the lifetime measurement can also be used for the measurement of the carrier concentration allowing excellent correlation between the lifetime and the doping concentration. The anodization techniques used for these measurements allow the stripping of small sections of even shallow diffused layers providing good depth resolution during the profiling. Using this method of lifetime profiling, lifetime measurements have been made up to concentrations of 1018atoms/cm3in both n- and p-type diffused layers in silicon. View full abstract»

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  • Measurements of residual defects and 1/f noise in ion-implanted p-channel MOSFET's

    Page(s): 478 - 484
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    This paper describes the measurements of excess noise and residual defects of extremely low concentrations (<1 × 109cm-2) in ion-implanted p-channel MOSFET's. The activation energy and the density of the residual defects after high-temperature annealing were measured using a transient capacitance technique. The test FET's were ion-implanted with fluences of 5 × 1011to 4 × 1012using31p+,11B+, or28Si+species. A post-implant anneal was carried out in an N2or an Ar ambient for 20 min at various temperatures. For11B+-implanted MOSFET's after annealing above 1000°C, a high residual defect concentration was observed near the conduction band edge; whereas after annealing the defect density as a result of28Si+or31p+implantation was equal to that of control MOSFET's. The density-of-state data agree with the equilibrium measurements of excess (1/f) noise power. The excess noise was measured as a function of the drain current. The distribution of1/fnoise power versus potential minimum of holes in the equilibrium condition is similar to that of interface state density. In nonequilibrium operation, a reduction of excess noise was achieved owing to the presence of buried channel created by ion implant. View full abstract»

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  • Diffusion length and lifetime determination in p-n junction solar cells and diodes by forward-biased capacitance measurements

    Page(s): 485 - 490
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    A new method is described and illustrated for determining the value and the temperature dependence of the minority-carrier diffusion length and lifetime in the base region of p-n junction solar cells and diodes. The method applies to devices after the p-n junction is formed, and thus includes the influence of the junction fabrication on the diffusion length and lifetime. The method requires only forward-biased capacitance measurements at the device terminals. It combines the dependencies of the low-frequency and high-frequency capacitance on forward bias in such a way as to yield the component of the capacitance associated with the minority carriers in the quasi-neutral base region. From this quasi-neutral-base capacitance the minority-carrier diffusion length and lifetime are then deduced. The accuracy of this method is estimated to be ±5 percent based on the accuracy of the capacitance bridges and of the measured temperature. To illustrate the method and its accuracy, it is applied to a set of silicon p-n junction diodes having base doping concentrations ranging from about 1014to 1018cm-3, and the values of the diffusion lengths determined by the capacitance method are compared with those obtained using the current response to X-ray excitation. Excellent agreement is seen. In contrast, the open-circuit-voltage-decay method yields values of the diffusion length that differ appreciably from those determined by the capacitance and X-ray methods. The reasons for the relative inaccuracy of the open-circuit-voltage-decay method applied to silicon devices are discussed. The practical limitations of the capacitance method are indicated, and an extension of the method is discussed that makes it applicable to devices having highly doped base regions and surface (emitter) layers. In such devices, the capacitance of the quasi-neutral emitter region can contribute appreciably to the total forward-biased capacitance, and the method can yield information about the material properties of the degenerately doped surface layer. The material properties determined are the phenomenological emitter lifetime and a measure of the energy bandgap narrowing in the emitter. View full abstract»

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  • An analysis of equivalent circuit with gate protection in MOS devices

    Page(s): 491 - 492
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    The dependence of the resistance associated with the equivalent circuit with gate protection on the electrical breakdown voltage was analyzed in terms of the transient solution of the equivalent circuit. The series resistance for the input voltage and the dynamic resistance in the breakdown region of the protective diode are found to have pronounced effects on the electrical breakdown voltage of the gate oxide, while the distributed resistance has a lesser effect on it. View full abstract»

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  • The effect of ionizing radiation on mobile ion current peaks in MOS capacitors

    Page(s): 492 - 494
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    MOS capacitors were examined for sodium ion concentrations before and after radiation using the high-temperature voltage ramp technique. The radiation caused a field-dependent lateral shift of the Na+displacement current peak along the voltage axis. An explanation is suggested based upon lateral nonuniformities and image forces. View full abstract»

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  • Comments on the emitter-current density dependence of popcorn noise frequency

    Page(s): 494 - 495
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    It has been found that the power spectrum of popcorn noise in integrated-circuit transistors can extend well into the audio-frequency range even at low emitter-current densities. View full abstract»

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  • Invention of p-n junction isolation in integrated circuits

    Page(s): 495 - 496
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    The origin of the p-n junction isolation technique is clarified, and certain allegations in a recent article by Kilby are repudiated. View full abstract»

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  • [Back cover]

    Page(s): c4
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology