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Electron Devices, IEEE Transactions on

Issue 5 • Date May 1977

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  • [Front cover and table of contents]

    Publication Year: 1977 , Page(s): c1
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    Freely Available from IEEE
  • Editorial

    Publication Year: 1977 , Page(s): 509 - 510
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  • Theory of MNOS memory transistor

    Publication Year: 1977 , Page(s): 511 - 518
    Cited by:  Papers (10)  |  Patents (1)
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    A theory on the switching behavior of the metal-Si3N4-SiO2-semiconductor (MNOS) memory transistor is presented which is consistent with the experimentally observed facts. The theory treats the switching process as being initially predominantly direct band-to-band tunneling and then dominated by modified-Fowler-Nordheim tunneling. The large-signal mathematical treatment includes both of these tunneling terms. The resultant charge-transport equation is rather complex; a numerical method is needed to obtain an exact solution, However, a grossly approximate closed-form solution has been obtained, which indicates that the transferred charge is initially a linear function of time and then logarithmic. This is similar to many of the previous theories. However, the coefficients in the current and charge solutions of the present theory contain the essential material, device, and operating parameters which are absent in previous theories. This makes the present model readily usable as a guide in the design and optimization of MNOS devices. View full abstract»

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  • Avalanche injection and near avalanche injection of charge carriers into SiO2

    Publication Year: 1977 , Page(s): 519 - 523
    Cited by:  Papers (4)  |  Patents (1)
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    A description is given of the avalanche injection of electrons from a p-n-junction into an adjacent SiO2layer. The resulting oxide current is found to decay due to the trapping of electrons in the SiO2. This decay can be characterized by the product of the concentration N of the trapping centers in the oxide and their capture cross section σ. We found N \sigma = 1.7 \times 10^{-1} cm-1. In addition, near avalanche injection is described. Here the oxide current is found to depend exponentially on the shortest acceleration distance of the hot carriers and is characterized by the mean free path of these carriers. A new result for the mean free path of the hot holes (λh= 42 Å) is given. Both types of injection find application in semiconductor memory cells. View full abstract»

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  • Charge transfer by direct tunneling in thin-oxide memory transistors

    Publication Year: 1977 , Page(s): 524 - 530
    Cited by:  Papers (5)
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    Charge transfer by direct tunneling in thin-oxide MNOS memory transistors is carefully examined and the similarities and dissimilarities between different models is shown. The consequences of different assumptions concerning the tunneling probability, surface states, and trap distributions are investigated, and directions for future work are discussed. View full abstract»

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  • Avalanche punch-through erase (APTE) mode in dual-dielectric charge-storage (DDC) cells

    Publication Year: 1977 , Page(s): 531 - 535
    Cited by:  Papers (1)
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    The erase of multilayer charge-storage memory cells by a reverse-bias pulsing of source and drain with the gate and substrate grounded has been previously suggested. Here the physical mechanisms behind this erase mode are explored. It is shown that both punch-through and avalanche are necessary for its operation. This avalanche punch-through erase (APTE) succeeds by pumping majority carriers into a potential pocket at the interface, thereby raising the interface surface potential to a level high enough to allow the stored charge to tunnel out. It is found experimentally that APTE is strongly affected by the lateral leakage of carriers from the pocket. Theoretical curves are presented which show how the pocket itself is affected by the cell geometry, doping level, and pulse amplitude. It appears that APTE is particularly suitable for reprogrammable read-often memories (REPROM's) using dual-dielectric memory cells (DDC/s) with interfacial dopant. These cells allow the use of a gate inhibit voltage pulse which is shown to increase the effectiveness of the APTE, making it a practical approach for random-access REPROM integrated circuits. View full abstract»

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  • Transient charge and current distributions in the nitride of MNOS devices

    Publication Year: 1977 , Page(s): 536 - 540
    Cited by:  Papers (5)
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    Transient charge distributions in the nitride of MNOS devices at constant-current pulses have been computed using the pronounced detrapping model of Arnett. The results are compared with available analytical expressions for the limiting cases of small injected-charge levels and the steady state. Centroid versus charge content is computed and fitted by an analytical expression containing three parameters which are related to the electron range before trapping, the steady-state occupied-trap concentration at the oxide boundary, and the Frenkel-Poole coefficient. Charge outflow into the gate electrode is computed and used to obtain the apparent centroid as derived from the shift of flat-band voltage with injected charge. View full abstract»

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  • A review of the techniques used to determine trap parameters in the MNOS structure

    Publication Year: 1977 , Page(s): 540 - 546
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    A series of experimental techniques based on the phenomenon of non-steady-state current flow during the dielectric relaxation of the MNOS device are examined. The non-steady-state currents are seen to be due to the response of traps in the different layers of the device, and the methods by which the correspondence between the peaks and the traps are determined are examined. Having established the correspondence it is seen that the trap parameters, both the energy distribution and the trap-capture cross sections, can be determined directly from experimental data. View full abstract»

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  • Auger depth profiling of MNOS structures by ion sputtering

    Publication Year: 1977 , Page(s): 547 - 551
    Cited by:  Papers (3)  |  Patents (3)
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    Auger electron spectroscopy has been used in conjunction with argon-ion sputtering to study the morphology and chemical nature of MNOS structures. We find that a typical thin "oxide" in a memory device is a silicon oxynitride with about equal parts nitrogen and oxygen. The transition from nitride to "oxide" to silicon is a smooth one, with an oxide width of about 2.5-nm FWHM. View full abstract»

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  • Charge-pumping investigations on MNOS structures

    Publication Year: 1977 , Page(s): 552 - 559
    Cited by:  Papers (1)
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    Charge-pump studies were performed on MNOS transistors. The well-known charge pumping due to surface states was observed. In addition, in source-drain protected structures, a well-pumping component was identified. The "scan-from-inversion" (SCI) concept was introduced for evaluation of these potential wells. View full abstract»

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  • Conditions for the absence of thermal breakdown in silicon nitride

    Publication Year: 1977 , Page(s): 559 - 564
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    Conditions for thermal current runaway and breakdown are investigated for the case when the temperature dependence of the electrical conductivity decreases with increasing field. Calculations show that thermal runaway does not arise at fields higher than an upper bound, even though large currents heat the insulator. Conditions found for the absence of thermal runaway are confirmed by experimental observations on silicon nitride. Unless the thermal conductance of the sample is poor and the electrical conductivity unusually large, thermal breakdown is not expected to arise in silicon nitride films. View full abstract»

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  • Test results on an MNOS memory array

    Publication Year: 1977 , Page(s): 564 - 568
    Cited by:  Papers (6)  |  Patents (1)
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    The NCR 2050 MNOS memory chip, developed under Air Force contract for frequency-preset applications in communications equipment, has been tested and evaluated. Results on retentivity, writing characteristics, pattern sensitivity, and endurance are presented. View full abstract»

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  • MNOS LSI memory device data retention measurements and projections

    Publication Year: 1977 , Page(s): 568 - 577
    Cited by:  Papers (7)  |  Patents (1)
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    The retention characteristics of an MNOS LSI memory device are interpreted from the properties of its basic MNOS transistor. A technique is developed for measuring and predicting retention properties of large quantity device lots. A production lot test method for determining the 10 000-h data retention properties of LSI memory devices is proposed. Also included in the paper are measured failure rates, identifying the retention failures and reliability for a specific LSI memory device. View full abstract»

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  • Endurance of thin-oxide nonvolatile MNOS memory transistors

    Publication Year: 1977 , Page(s): 577 - 580
    Cited by:  Papers (13)
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    A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3N4dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 1010erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time. View full abstract»

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  • A method of tungsten dopant deposition for dual-dielectric charge-storage cells

    Publication Year: 1977 , Page(s): 581 - 583
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    Electron-beam evaporation of small single-crystal ingots of tungsten has been employed as a laboratory-scale method for introducing the tungsten interfacial dopant in dual-dielectric charge-storage cells. Several other tungsten-evaporation methods, which are potentially more suitable for large-scale manufacturing operations, are evaluated. They are: 1) evaporation from resistively heated tungsten; 2) evaporation of tungsten trioxide powder from a resistively heated crucible; and 3) reactive evaporation of tungsten trioxide from resistively heated tungsten in a low-pressure ambient of oxygen. The latter method, which seemed the most attractive, was tested and was found to be a practical alternative to the electron-beam method. It possesses the advantages of low operating temperatures, control of small deposition rates to produce tungsten trioxide deposits in the submonolayer range of coverage, pure deposits, and requires a minimum of operator attention. Furthermore, sources can have a long operating life. View full abstract»

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  • Threshold-alterable Si-gate MOS devices

    Publication Year: 1977 , Page(s): 584 - 586
    Cited by:  Papers (9)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    An electrically threshold-alterable n-channel MOS device with polysilicon gate is experimentally realized by employing a polysilicon-oxynitride-nitride-oxide-silicon (SONOS) structure. Because of several high-temperature processing steps after the nitride deposition, it was found necessary to increase the thin-oxide thickness of the SONOS devices in order to achieve better charge retentivity. It has been shown that the SONOS device can be used in MOS integrated circuits. Some memory and switching characteristics of the SONOS devices with oxide thickness of ∼30 Å are presented. View full abstract»

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  • Fatigue phenomena of FTMIS memory transistors

    Publication Year: 1977 , Page(s): 587 - 590
    Cited by:  Papers (3)
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    Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 Å) SiO2. The floating gate consists of highly resistive polycrystalline Si grains. Gate oxidation isolates each poly-Si grain, resulting in a structure of islands. This improves retention characteristics. The primary feature of these devices is that no fatigue phenomena are observed for 2 × 1012cycles continuous write-erase operation in the conventional operation mode. In addition, it is possible both to write and erase in the other operation mode with only positive pulses to the gate electrode. Furthermore, stored data is retained more than one year without any external power supply. Therefore the device is an excellent candidate for nonvolatile RAM applications as a semiconductor memory device. View full abstract»

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  • Some characteristics of nonvolatile CdSe thin-film memory transistors

    Publication Year: 1977 , Page(s): 591 - 593
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    Improvement on CdSe thin-film memory transistors was made by optimizing the deposition condition of aluminum interfacial dopant (IFD) between the two dielectric insulators of the gate. Threshold voltage window of the devices was optimized at IFD thickness of about 10 to 20 Å and was found to increase with IFD deposition rate. Charging speed of the optimized devices was improved by an order of magnitude over previously unoptimized devices. View full abstract»

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  • DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

    Publication Year: 1977 , Page(s): 594 - 599
    Cited by:  Papers (14)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques. View full abstract»

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  • Technology of a new n-channel one-transistor EAROM cell called SIMOS

    Publication Year: 1977 , Page(s): 600 - 606
    Cited by:  Papers (10)  |  Patents (8)
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    The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected into the floating gate. On account of the channel-injection mechanism performed in the programming mode, channel lengths of less than 4 µm are required. A combination of this condition with the stacked-gate concept is achieved by a self-aligned technique which defines both polysilicon gates by a single photolithographic procedure. By means of the self-aligned technique, both the one-transistor EPROM cell and the one-transistor EAROM cell can be realized. Basic structures of the two different type one-transistor memory cells are the SIMOS transistor and the SIMOS tetrode, respectively. The technology of these two different SIMOS devices is described in detail and experimental results concerning charge accumulation, charge removal, and charge retention are reported. View full abstract»

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  • Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

    Publication Year: 1977 , Page(s): 606 - 610
    Cited by:  Papers (12)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm2. The photograph of a fully decoded 8192-bit SIMOS memory chip is presented. View full abstract»

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  • A 4096-bit word-alterable ROM

    Publication Year: 1977 , Page(s): 610 - 613
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    The organization and operation of a 4096-bit MNOS word-alterable ROM is described. The device is primarily intended for ROM program storage with electrically alterable capability. However, it can also be used for slow-speed RAM applications where the number of erase-write cycles does not exceed 105per word. Margining means are provided which can predict the device remanence for various erase and write times and reading conditions. View full abstract»

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  • Electrically erasable buried-gate nonvolatile read-only memory

    Publication Year: 1977 , Page(s): 613 - 618
    Cited by:  Papers (3)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    An electrically erasable buried (floating) gate memory is described. The memory is programmed by electron injection by junction avalanche. An internal voltage multiplication scheme using varactor bootstrapping is used which makes nearly 40 V available at the memory cell for programming, yet requires input voltages no higher than 25 V. Erasure takes place by modified Poole-Frenkel conduction in a Si3N4film of 700-Å thickness which overlays the buried gate. Standard silicon gate p-MOS processing is used with only minor modifications. Memory retention is excellent and is extrapolated to many years even at 150°C. Above 298 K, the time required for the charge to decay to one-half its initial value is given by \log t_{1/2} = \frac{5254}{T}-\frac{771}{T}\sqrt{V_{E}}(s) where T (K) is the temperature and VEis the erase voltage. The endurance of the buried-gate memory is approximately 10 K write-erase cycles and is limited by electron trapping in the insulator. A fully decoded 1024-bit memory chip was designed and fabricated. View full abstract»

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  • MNOS density parameters

    Publication Year: 1977 , Page(s): 618 - 625
    Cited by:  Papers (2)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    Some aspects of the feasibility of the MNOS technology for the realization of large read/write memory systems are examined. Contemporary and near term density parameters for volume, weight, and power are presented. Achievable memory cells and die sizes are examined. The impact of nonvolatility on system reliability is explained. Packaging density forchip assemblies and memory systems is reviewed. Finally, the parameters and reliability of a 109bit MNOS memory are described. View full abstract»

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  • [Back cover]

    Publication Year: 1977 , Page(s): c4
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    Freely Available from IEEE

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

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University of California San Diego