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IEEE Transactions on Electron Devices

Issue 5 • Date May 1977

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Displaying Results 1 - 25 of 25
  • [Front cover and table of contents]

    Publication Year: 1977, Page(s): c1
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  • Editorial

    Publication Year: 1977, Page(s):509 - 510
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  • Theory of MNOS memory transistor

    Publication Year: 1977, Page(s):511 - 518
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    A theory on the switching behavior of the metal-Si3N4-SiO2-semiconductor (MNOS) memory transistor is presented which is consistent with the experimentally observed facts. The theory treats the switching process as being initially predominantly direct band-to-band tunneling and then dominated by modified-Fowler-Nordheim tunneling. The large-signal mathematical treat... View full abstract»

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  • Avalanche injection and near avalanche injection of charge carriers into SiO2

    Publication Year: 1977, Page(s):519 - 523
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A description is given of the avalanche injection of electrons from a p-n-junction into an adjacent SiO2layer. The resulting oxide current is found to decay due to the trapping of electrons in the SiO2. This decay can be characterized by the product of the concentration ... View full abstract»

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  • Charge transfer by direct tunneling in thin-oxide memory transistors

    Publication Year: 1977, Page(s):524 - 530
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    Charge transfer by direct tunneling in thin-oxide MNOS memory transistors is carefully examined and the similarities and dissimilarities between different models is shown. The consequences of different assumptions concerning the tunneling probability, surface states, and trap distributions are investigated, and directions for future work are discussed. View full abstract»

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  • Avalanche punch-through erase (APTE) mode in dual-dielectric charge-storage (DDC) cells

    Publication Year: 1977, Page(s):531 - 535
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The erase of multilayer charge-storage memory cells by a reverse-bias pulsing of source and drain with the gate and substrate grounded has been previously suggested. Here the physical mechanisms behind this erase mode are explored. It is shown that both punch-through and avalanche are necessary for its operation. This avalanche punch-through erase (APTE) succeeds by pumping majority carriers into ... View full abstract»

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  • Transient charge and current distributions in the nitride of MNOS devices

    Publication Year: 1977, Page(s):536 - 540
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Transient charge distributions in the nitride of MNOS devices at constant-current pulses have been computed using the pronounced detrapping model of Arnett. The results are compared with available analytical expressions for the limiting cases of small injected-charge levels and the steady state. Centroid versus charge content is computed and fitted by an analytical expression containing three para... View full abstract»

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  • A review of the techniques used to determine trap parameters in the MNOS structure

    Publication Year: 1977, Page(s):540 - 546
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A series of experimental techniques based on the phenomenon of non-steady-state current flow during the dielectric relaxation of the MNOS device are examined. The non-steady-state currents are seen to be due to the response of traps in the different layers of the device, and the methods by which the correspondence between the peaks and the traps are determined are examined. Having established the ... View full abstract»

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  • Auger depth profiling of MNOS structures by ion sputtering

    Publication Year: 1977, Page(s):547 - 551
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Auger electron spectroscopy has been used in conjunction with argon-ion sputtering to study the morphology and chemical nature of MNOS structures. We find that a typical thin "oxide" in a memory device is a silicon oxynitride with about equal parts nitrogen and oxygen. The transition from nitride to "oxide" to silicon is a smooth one, with an oxide width of about 2.5-nm FWHM. View full abstract»

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  • Charge-pumping investigations on MNOS structures

    Publication Year: 1977, Page(s):552 - 559
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Charge-pump studies were performed on MNOS transistors. The well-known charge pumping due to surface states was observed. In addition, in source-drain protected structures, a well-pumping component was identified. The "scan-from-inversion" (SCI) concept was introduced for evaluation of these potential wells. View full abstract»

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  • Conditions for the absence of thermal breakdown in silicon nitride

    Publication Year: 1977, Page(s):559 - 564
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Conditions for thermal current runaway and breakdown are investigated for the case when the temperature dependence of the electrical conductivity decreases with increasing field. Calculations show that thermal runaway does not arise at fields higher than an upper bound, even though large currents heat the insulator. Conditions found for the absence of thermal runaway are confirmed by experimental ... View full abstract»

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  • Test results on an MNOS memory array

    Publication Year: 1977, Page(s):564 - 568
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The NCR 2050 MNOS memory chip, developed under Air Force contract for frequency-preset applications in communications equipment, has been tested and evaluated. Results on retentivity, writing characteristics, pattern sensitivity, and endurance are presented. View full abstract»

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  • MNOS LSI memory device data retention measurements and projections

    Publication Year: 1977, Page(s):568 - 577
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The retention characteristics of an MNOS LSI memory device are interpreted from the properties of its basic MNOS transistor. A technique is developed for measuring and predicting retention properties of large quantity device lots. A production lot test method for determining the 10 000-h data retention properties of LSI memory devices is proposed. Also included in the paper are measured failure ra... View full abstract»

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  • Endurance of thin-oxide nonvolatile MNOS memory transistors

    Publication Year: 1977, Page(s):577 - 580
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, diele... View full abstract»

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  • A method of tungsten dopant deposition for dual-dielectric charge-storage cells

    Publication Year: 1977, Page(s):581 - 583
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Electron-beam evaporation of small single-crystal ingots of tungsten has been employed as a laboratory-scale method for introducing the tungsten interfacial dopant in dual-dielectric charge-storage cells. Several other tungsten-evaporation methods, which are potentially more suitable for large-scale manufacturing operations, are evaluated. They are: 1) evaporation from resistively heated tungsten;... View full abstract»

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  • Threshold-alterable Si-gate MOS devices

    Publication Year: 1977, Page(s):584 - 586
    Cited by:  Papers (9)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    An electrically threshold-alterable n-channel MOS device with polysilicon gate is experimentally realized by employing a polysilicon-oxynitride-nitride-oxide-silicon (SONOS) structure. Because of several high-temperature processing steps after the nitride deposition, it was found necessary to increase the thin-oxide thickness of the SONOS devices in order to achieve better charge retentivity. It h... View full abstract»

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  • Fatigue phenomena of FTMIS memory transistors

    Publication Year: 1977, Page(s):587 - 590
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 Å) SiO2. The floating gate consists of highly resistive poly... View full abstract»

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  • Some characteristics of nonvolatile CdSe thin-film memory transistors

    Publication Year: 1977, Page(s):591 - 593
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Improvement on CdSe thin-film memory transistors was made by optimizing the deposition condition of aluminum interfacial dopant (IFD) between the two dielectric insulators of the gate. Threshold voltage window of the devices was optimized at IFD thickness of about 10 to 20 Å and was found to increase with IFD deposition rate. Charging speed of the optimized devices was improved by an order of... View full abstract»

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  • DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

    Publication Year: 1977, Page(s):594 - 599
    Cited by:  Papers (16)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons t... View full abstract»

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  • Technology of a new n-channel one-transistor EAROM cell called SIMOS

    Publication Year: 1977, Page(s):600 - 606
    Cited by:  Papers (10)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB)

    The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected in... View full abstract»

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  • Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

    Publication Year: 1977, Page(s):606 - 610
    Cited by:  Papers (12)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can b... View full abstract»

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  • A 4096-bit word-alterable ROM

    Publication Year: 1977, Page(s):610 - 613
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The organization and operation of a 4096-bit MNOS word-alterable ROM is described. The device is primarily intended for ROM program storage with electrically alterable capability. However, it can also be used for slow-speed RAM applications where the number of erase-write cycles does not exceed 105per word. Margining means are provided which can predict the device remanence for various ... View full abstract»

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  • Electrically erasable buried-gate nonvolatile read-only memory

    Publication Year: 1977, Page(s):613 - 618
    Cited by:  Papers (3)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    An electrically erasable buried (floating) gate memory is described. The memory is programmed by electron injection by junction avalanche. An internal voltage multiplication scheme using varactor bootstrapping is used which makes nearly 40 V available at the memory cell for programming, yet requires input voltages no higher than 25 V. Erasure takes place by modified Poole-Frenkel conduction in a S... View full abstract»

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  • MNOS density parameters

    Publication Year: 1977, Page(s):618 - 625
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    Some aspects of the feasibility of the MNOS technology for the realization of large read/write memory systems are examined. Contemporary and near term density parameters for volume, weight, and power are presented. Achievable memory cells and die sizes are examined. The impact of nonvolatility on system reliability is explained. Packaging density forchip assemblies and memory systems is reviewed. ... View full abstract»

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  • [Back cover]

    Publication Year: 1977, Page(s): c4
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

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Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy

Phone +39 011 090 4064
email giovanni.ghione@polito.it