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Electron Devices, IEEE Transactions on

Issue 9 • Date Sept. 1976

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Displaying Results 1 - 25 of 33
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Field-enhanced space-charge-limited hole currents in thin-oxide MNOS varactors

    Page(s): 995 - 997
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    This paper describes the results of an investigation of hole currents in the thin-oxide metal-silicon nitride-silicon dioxide-silicon (MNOS) varactor structure. Deviations from the predictions of Poole-Frenkel theory were noted. The results were analyzed using the calculations of Murgatroyd for space-charge-limited (SCL) flow, suitably modified to account for a threshold of SCL current due to the oxide potential barrier. The result is shown to agree with experiment over approximately six decades of current while traditional space-charge-free Poole-Frenkel theory does not. View full abstract»

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  • Noise effects in bipolar junction transistors at cryogenic temperatures: Part I

    Page(s): 998 - 1007
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    Part I of this investigation involves theoretical and experimental characterization of the noise performance of modern silicon planar bipolar junction transistors (BJT's) above the 1/f noise frequency region in a temperature range of 60-300 K and for several difference bias conditions. At temperatures below approximately 110 K, an excess noise source as measured by the equivalent noise resistance RN, referred to the input of the device, common-base configuration, is revealed. This excess source, resulting from a generation-recombination process within the base region of the device, is shown to have a linear dependence on the base current and base resistance as KIB2rb'b2, and an exponential dependence on temperature. View full abstract»

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  • Noise effects in bipolar junction transistors at cryogenic temperatures: Part II

    Page(s): 1007 - 1011
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    In Part II of this investigation, a characterization of the output noise current generator i0of modern planar bipolar junction transistors (BJT's) for common-base configuration with the input ac open circuited is developed and verified at temperatures ranging from 60 to 300 K. It is shown that at low temperatures, for those devices where recombination processes in the emitter-base space-charge region become very pronounced, the resulting noise for these processes shows less than full shot noise. This noise reduction can show up at temperatures slightly below room temperature for such devices. (Generation-recombination effects described in Part I may still become important at temperatures below 110 K.) Also, it is demonstrated that an important parameter to monitor in taking these measurements, at least at low temperatures, is the alpha cutoff frequency fα if the low-frequency theory is to be realized. View full abstract»

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  • Dynamic cathode boundary fields and transferred electron oscillators

    Page(s): 1012 - 1015
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    The evolution of a generalized time-dependent cathode boundary field model is discussed, and calculations are presented which demonstrate its applicability for explaining such diverse phenomena as 1) the appearance of anomalously high efficiency oscillations in InP and 2) the more moderate oscillatory behavior associated with GaAs. View full abstract»

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  • Avalanche breakdown characteristics of punchthrough diodes

    Page(s): 1016 - 1023
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    A theoretical investigation of the avalanche breakdown characteristics of punchthrough diodes is carried out and a comparison made with the nonpunchthrough diodes. It is shown that the former have harder breakdown characteristics and a sharper knee for a given breakdown voltage. In addition, punchthrough diodes have a lower temperature coefficient of breakdown voltage, a lower space-charge resistance, a negligible sensitivity of breakdown voltage to resistivity striations in single crystal wafers, and breakdown due to avalanche mechanism up to lower breakdown voltages. Though these positive features suggest that punchthrough diodes are superior in performance to nonpunchthrough diodes for applications such as voltage regulators etc., the final assessment will depend on a more critical evaluation of the reliability against burn out and instability. View full abstract»

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  • Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

    Page(s): 1023 - 1027
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    As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with31P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by31P and11B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with31P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm2. View full abstract»

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  • Bistable switching in supercritical n+-n-n+GaAs transferred electron devices

    Page(s): 1028 - 1035
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    Bistable switching in supercritically doped n+-n-n+GaAs transferred electron devices (TED's) is investigated experimentally and interpreted in computer simulations, for which details of the computer program are given. Three switching modes all leading to stable anode domains are discussed, namely: 1) cathode-triggered traveling domain; 2) cathode-triggered accumulation layer; 3) anode-triggered domain. Relative current drops up to 40 percent, and switching times down to 60 ps are obtained in low-duty-cycle pulsed experiments with threshold currents around 400 mA. Optimum device parameters are shown to be as follows: 1) doping in the 3-4 × 1015cm-3range; 2) length around 6 µm; 3) doping gradients below 20 percent; 4) high-quality interfaces. View full abstract»

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  • New two-terminal C-MNOS memory cells

    Page(s): 1036 - 1041
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    New two-terminal nonvolatile memory cells are proposed, in which an n-channel MNOS transistor is functionally integrated with a p-channel MNOS or MOS transistor. The operational principle of both types of the cells is substantially based on the Λ (lambda)-shaped I-V Characteristic of complementary FET's. The most valuable feature of the new cells is the unipolar pulse operation of the simple diode-matrix array which can be used in a RAM mode by the use of selective writing and erasing as well as in an electrically alterable PROM mode. View full abstract»

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  • Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates

    Page(s): 1042 - 1048
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    Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis. View full abstract»

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  • Trigger sensitivity of transferred electron logic devices

    Page(s): 1049 - 1052
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    An analysis of the Schottky-barrier gate transferred electron logic devices (TELD's) is developed which gives the trigger sensitivity in terms of the channel pinchoff voltage, normalized channel depletion width under the gate, device subthreshold transconductance, and the value of the external load resistor. The results presented show that the trigger sensitivity increases with increase in doping density, decrease in channel pinchoff voltage, and decrease in gate reverse bias. Furthermore, for the same material parameters (doping density, channel thickness, etc.) device subthreshold transconductance (gm) improves the trigger sensitivity by a factor (1 + gmRL). Device designs based on this analysis should result in improved device performance. View full abstract»

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  • An application of acoustic surface wave devices to communication receivers

    Page(s): 1053 - 1057
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    In this paper we present a new acoustic surface wave phase-locked loop FM demodulator. This device uses the nonlinear coupling characteristics of an insulating piezoelectric to an adjacent semiconductor to generate an electric field in the semiconductor. The low-frequency voltage resulting from the spatial integration of the electric field along the semiconductor is used as the controlling voltage of a voltage controlled oscillator. The above device acts as a phase-locked loop of either the first order or the second order, depending on the amplitude of the input waves, the characteristics of the coupling device, and the integration length of the electric field in the semiconductor. Both theoretical and experimental results relating to the lock range, frequency tracking, and FM demodulation characteristics of the novel device are described. View full abstract»

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  • A new and simple light-pen position-detection technique for interactive plasma-display systems

    Page(s): 1058 - 1063
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    The plasma panel is a 2-level type of display possessing local memory, high luminance, and selective write-erase capability. There are, however, no convenient inexpensive methods for interacting graphically with material displayed on a panel by means of a hand-held stylus. A simple and potentially low-cost technique has been developed in which a light pen can be used to point at any part, dark or light, of a plasma panel, thus making an economical interactive plasma-display system possible. The technique is based on the ability to selectively address one cell of the panel with a sequence of two interrogating pulses. Therefore, depending on the state of the addressed cell, one or the other interrogating pulse will cause the addressed cell to flash at a time different from all other cells, without altering the state of the addressed cell or disturbing the unselected cells. The light pen is gated to look for these light pulses and their individual Phase in order to establish the location of the light pen and the state of the cell. The operating margins for the interrogating pulses exceed the panel's own write-erase margins, and the additional hardware required beyond the normal panel sustain and select circuitry is negligible. View full abstract»

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  • Influence of carrier diffusion on an anode trapped domain formation in a transferred electron device

    Page(s): 1063 - 1069
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    This paper presents an influence of the electric field dependence of the diffusion coefficient of electrons (D(E) relation) on a formation of a stable domain at an anode contact in a transferred electron device. The stable domain (anode trapped domain) has been observed in a planar Gunn device experimentally, and it has been shown that a large trigger voltage is needed to launch a new domain if a preceding domain has been trapped. Computer simulations have been carried out in order to find a condition to form the trapped domain. Various D(E) relations of GaAs presented by many authors have been adopted to the simulation, and it is shown that one of these D(E) relations is suitable to describe the dynamic behaviors of electrons in GaAs. Simulated results have indicated that the trapped domain occurs in a certain range of doping density. View full abstract»

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  • Concentration profiles of recombination centers in semiconductor junctions evaluated from capacitance transients

    Page(s): 1069 - 1074
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    The effect of stationary charges trapped in the region near the p-n boundary and in the edge region of a semiconductor junction space-charge layer on the evaluation of the concentration profiles of the recombination centers as well as doping impurities, from high-frequency capacitance transient data, is studied. Both the theory, its simplification for junctions with low concentration of recombination centers, and two experimental examples are given to illustrate the importance of the edge effect. One of the examples is an aluminum on n-Si Schottky diode with a very low concentration of process-induced donor trap, and the other is a phosphorus and gold diffused diode with a gold concentration about 20 percent of the boron concentration. View full abstract»

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  • Noise in gallium arsenide avalanche Read diodes

    Page(s): 1075 - 1085
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    The noise and signal properties of Read-type avalanche diodes under large-signal levels are examined. In contrast to most other previous theories, we include the saturation current in the equations rigorously from the beginning. We find that the noise performance is a strong function of the saturation current such that high saturation currents lead to lower noise performance. We compare the findings of our model with measurements on two very different Read-type avalanche diodes with a low-high-low profile. In agreement with theory, the lower noise diode has a higher saturation current. We also find experimentally that the noise measure of the diodes used as oscillators decreases with increasing power output. This feature is explained by the rising reverse saturation current with temperature which in some diodes more than compensates the normally increasing noise measure with power output. View full abstract»

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  • The noise measure of GaAs and InP transferred electron amplifiers

    Page(s): 1086 - 1094
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    The noise measures of both GaAs and InP transferred electron amplifiers (TEA's) are calculated by a small-signal computer simulation for devices having a range of realistic doping profiles, some of which are designed specifically to limit the amount of free charge injected into the structure. Optimum values of average electric-field strength and carrier concentration times length product for minimum noise are shown to exist. The computed results differ not too greatly from those predicted by a simple analytical model where a uniform free carrier concentration and dc electric field are assumed. The lowest noise measures predicted are 7 dB for GaAs and 4 dB for InP if charge injection is suitably constrained. The computed results are compared with results reported in the literature. View full abstract»

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  • A note on carrier densities in p-n junctions

    Page(s): 1094 - 1095
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    The accuracy of the Boltzmann relation for the derivation of p-n junction forward characteristics is examined by relatively simple analysis, when recombinations in the depletion layer are negligible. The Boltzmann relation for carrier densities is found to be applicable in wide-base diodes, but in thin-base diodes and transistors, carrier densities can be smaller than those calculated with the Boltzmann relation. View full abstract»

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  • Redistribution of ion-implanted impurities in silicon during diffusion in oxidizing ambients

    Page(s): 1095 - 1097
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    A closed form expression for the redistribution of ion-implanted impurities in silicon during diffusion in an oxidizing ambient is derived, based on a theoretical model proposed by Huang and Welliver. It is shown that the computed results for boron profiles agree very well with experimental data. The closed form solution requires considerably less computer execution time than the usual numerical solution. View full abstract»

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  • JFET-transistor yields device with negative resistance

    Page(s): 1098 - 1099
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    A composite p-channel ion implanted JFET and an n-p-n bipolar transistor which exhibits a negative resistance region and a positive feedback path is described in this correspondence. View full abstract»

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  • FET circuit destruction caused by electrostatic discharge

    Page(s): 1099 - 1103
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    Under certain environmental conditions, electrostatic discharges can cause catastrophic failure in both bipolar and FET integrated circuits [1]. Some devices (MOSFET's) are particularly susceptible to damage because of the relatively low destructive breakdown voltage (50 to 100 V) of their thin oxides. One source of concern is discharges from the human body during handling. This problem can be minimized by taking various approaches, such as 1) manufacturing the device so it has a high oxide breakdown voltage, 2) adding a protective device to the input, 3) developing special handling procedures to prevent high voltages from being applied to the devices accidentally. The objectives of this paper are to present a technique to test the effectiveness of FET protective devices using a simulated human static discharge and also to present a mathematical model that can predict a catastrophic failure as a function of voltage developed across the FET device and the energy dissipated. Both theoretical and experimental data are presented. View full abstract»

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  • Sequential anneal effect on bipolar transistor with phosphorus-implanted emitter

    Page(s): 1103 - 1104
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    An n-p-n-type bipolar transistor with an emitter region formed by a new ion implantation predeposition diffusion exhibits much less leakage current compared to that formed by a conventional process. This new emitter region has a thermal history of first anneal at 500°C, second anneal at 900°C, and third anneal at 1050°C after phosphorus implantation predeposition of 1 × 1016/cm2at 50 keV. View full abstract»

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  • Matrix-array cathode ray tube

    Page(s): 1105 - 1106
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    A flat matrix-array cathode-ray tube that has the potential of producing very bright displays is described. This tube combines electron beams and thin-film transistors within one vacuum envelope. Construction and performance of a demonstration device is discussed. View full abstract»

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  • An efficient passivated TRAPATT diode structure

    Page(s): 1107 - 1108
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    A TRAPATT diode has been fabricated using a variation of silicon planar technology. Its design combines the advantages of the surface stability of the planar process with low parasitic capacitance usually associated only with mesa devices. Since shallow diffusions may be used, the device retains an excellent heat-dissipation capability. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology