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Solid-State Circuits, IEEE Journal of

Issue 3 • Date June 1990

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Displaying Results 1 - 25 of 40
  • Front cover - IEEE Journal of Solid-State Circuits

    Publication Year: 1990 , Page(s): c1
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    Freely Available from IEEE
  • Race-free clocking of CMOS pipelines using a single global clock

    Publication Year: 1990 , Page(s): 766 - 769
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    A novel, single-phase, race-free CMOS circuit clocking technique, which provides and uses complementary logic, is presented. The clock can be driven by a sinusoidal waveform. This avoids any requirement for transmitting the very-high-frequency components associated with fast clock edges. Such circuits are therefore less sensitive to clock distortion caused by transmission-line effects View full abstract»

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  • Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits

    Publication Year: 1990 , Page(s): 863 - 865
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    Driver configurations and full-swing techniques for several types of BiCMOS logic circuits are compared to examine their performance in scaled technologies. Of the three driver configurations (common emitter, gated diode, and emitter follower) analyzed, the emitter-follower type is most advantageous for scale power-supply voltage circuits. Full-swing techniques boost the circuit performance, and base-emitter shunting is more favorable than collector-emitter shunting View full abstract»

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  • A single-chip 5-V 2400-b/s modem

    Publication Year: 1990 , Page(s): 632 - 643
    Cited by:  Papers (1)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The receiver is performed almost entirely in the analog domain. The IC also supports a number of lower-speed (⩽1200 b/s) split-band modem standards. The chip occupies 68.8 mm2 and dissipates 120 mW while operating off a single 5-V supply. System and circuit aspects of the design are discussed, and the measured performance of the IC is summarized View full abstract»

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  • Ganged CMOS: trading standby power for speed

    Publication Year: 1990 , Page(s): 870 - 873
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    The authors present ganged-CMOS logic (GCMOS), a technique employing CMOS inverters with their outputs shorted together, driving one or more encoding inverters. These encoding inverters, serving to quantize the nonbinary signal at the ganged node, effectively buffer it from external circuitry, thus allowing locally smaller noise margins. As demonstrated by two novel adders, GCMOS achieves higher speeds and lower input capacitances than static CMOS, at the expense of higher static power dissipation. Monte Carlo simulations have shown that extremely tight process control is not needed to ensure correct operation; however, it is required to obtain optimum circuit performance View full abstract»

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  • A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

    Publication Year: 1990 , Page(s): 866 - 870
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    An efficient strategy for utilizing a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAMs (dynamic random-access memories) is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log2w+2 in the conventional Hamming code. Such an error-correction circuit significantly improves the reliability of the memory system View full abstract»

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  • Pipelined architecture for fast CMOS buffer RAMs

    Publication Year: 1990 , Page(s): 741 - 747
    Cited by:  Papers (11)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts View full abstract»

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  • A 1.544-Mb/s CMOS line driver for a 22.8-Ω load

    Publication Year: 1990 , Page(s): 760 - 763
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 Vpp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm2 using a 2-μm p-well CMOS technology View full abstract»

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  • A high slew-rate CMOS amplifier for analog signal processing

    Publication Year: 1990 , Page(s): 885 - 889
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The performances of several types of analog VLSI circuits are limited by the setting behavior of CMOS amplifiers. An amplifier with a nonsaturated input stage which achieves a high slew-rate response is presented. The impact of this slew-rate amplifier on switched-capacitor circuits is described. Prototyping amplifier circuits were fabricated by the MOSIS service using a 2-μm scalable CMOS technology. When biased at a DC power dissipation of 1 mW, the two-stage amplifier achieves a slew rate of 80 V/μs, a positive-supply rejection ratio of 73 dB, and a negative-supply rejection ratio of 57 dB and 50 kHz View full abstract»

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  • A 700-V interface IC for power bridge circuits

    Publication Year: 1990 , Page(s): 677 - 683
    Cited by:  Papers (5)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A 700-V integrated interface circuit is presented. It provides the gate drive for the high-side and the ground-side power MOS transistor in an offline half-bridge circuit. Ground separation for good intersystem electromagnetic compatibility (EMC) and a number of new provisions to alleviate control requirements on the low-power system control section are included. An electronic ballast for gas discharge lamps is considered as an application example. Experimental results are presented View full abstract»

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  • Transistor-only frequency-selective circuits

    Publication Year: 1990 , Page(s): 821 - 832
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1104 KB)  

    The possibility of implementing frequency-selective circuits using only MOS transistors is considered. The advantages of such circuits are small chip area, good matching properties for individual elements, a potential for very high frequency of operation, and suitability for fabrication using standard digital VLSI processes. Disadvantages include the implementation of automatic tuning schemes that reliably eliminate unpredictabilities and variations, device modeling difficulties of common simulators, and nonlinearity cancellation. A procedure for the topology development of filters in which transistors are used as URC elements is presented together with a technique which uses transistors as capacitors, along with first-order correction for the nonidealities of such `capacitors' and of the active elements. Measured results from three experimental chips are reported in the 1-100-MHz range View full abstract»

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  • A 54-MHz CMOS programmable video signal processor for HDTV applications

    Publication Year: 1990 , Page(s): 730 - 734
    Cited by:  Papers (7)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency View full abstract»

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  • Implementation of switch network logic in SOI

    Publication Year: 1990 , Page(s): 874 - 877
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    Implementation of switch network logic (SNL) in silicon-on-insulator (SOI) technology is examined. The effect of substrate connection is considered in order to examine the behavior of MOSFET as a switch. A situation that causes an extremely high leakage current through the substrate is discussed. This large current through the substrate restricts the switch-level modeling for SOI MOSFETs and hence the SNL implementation. A simple procedure is presented that provides an optimized design for SOI implementation View full abstract»

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  • Low-noise, low-distortion CMOS AM wide-band amplifiers matching a capacitive source

    Publication Year: 1990 , Page(s): 833 - 840
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A low-noise, low-distortion AM wideband CMOS amplifier that matches a capacitive antenna is presented. The amplifier uses a single-ended input stage to realize optimal noise matching with a capacitive source of 75 pF. The equivalent input noise voltage is as low as 0.7 μVrms within 2.5-kHz IF (intermediate frequency) bandwidth. A differential symmetrical class-AB output stage is optimized to large-scale signal distortion performance. With an 8-V single-power supply the amplifier is capable of driving a 7-Vpp/1-MHz signal into a 400-Ω load with a total harmonic distortion of 2%. A very high dynamic range of 130 dB has thus been achieved. An intermodulation-free dynamic range up to 96 dB and an IM3 intercept of 18 Vpp have been measured. The amplifier is fabricated in a standard 3-μm n-well CMOS technology. Design details concerning noise, distortion, and stability performance are analytically described View full abstract»

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  • A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

    Publication Year: 1990 , Page(s): 748 - 756
    Cited by:  Papers (52)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm2 in a 2-μm CMOS process and 500 mW at 25 MHz) View full abstract»

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  • A new low-noise 100-MHz balanced relaxation oscillator

    Publication Year: 1990 , Page(s): 692 - 698
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A novel fully balanced architecture for high-frequency, low-noise relaxation oscillators is presented. Differential operation is achieved with the use of two grounded capacitors utilizing the circuit parasitics. Bypassing of the regenerative memory function in the oscillator benefits both high-speed and low-noise operation. A detailed analysis of phase noise in relaxation oscillators is performed. Results obtained from a test chip have verified the viability of the new oscillator and the developed phase-noise theory. The oscillator circuit has been realized in a medium-frequency (fτ=3 GHz) bipolar process. The tuning range extends to 150 MHz. At an oscillation frequency of 115 MHz, measured phase noise was -118 dBc/Hz at 1-MHz distance from the carrier View full abstract»

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  • A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocell library

    Publication Year: 1990 , Page(s): 770 - 777
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm2 die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz View full abstract»

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  • Realization of a three-valued logic built-in testing structure

    Publication Year: 1990 , Page(s): 814 - 820
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    It is argued that the practical realization of n-valued logic (n⩾3) built-in testing circuits is not an obvious extension of the binary case. To support this claim, the implementation of a testing technique for ternary CMOS VLSI circuits is presented. A three-valued logic built-in logic block observer (BILBO) has been engineered to operate in four modes: reset, normal, scan path, and signature analysis. The main objective is to provide a method of design and implementation of three-valued logic circuits that are easy to test and able to test themselves. BILBO allows both random testing (signature analysis) and deterministic testing (selected test vectors) View full abstract»

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  • Influence of transmission-line interconnections between gigabit-per-second ICs on time jitter and instabilities

    Publication Year: 1990 , Page(s): 763 - 766
    Cited by:  Papers (26)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    The influence of transmission-line interconnections between high-speed ICs on time jitter and oscillations is investigated. Simple but flexible methods for estimating these effects are proposed and proved by measurements and simulations. The estimations are based on small-signal reflection coefficients. Moreover, various line terminations are discussed. A special gigabit-per-second bipolar IC was fabricated for the experiments View full abstract»

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  • Op amp combining precision, high speed, and high output current drive for ±5-V power supply operation

    Publication Year: 1990 , Page(s): 856 - 862
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    A monolithic operational amplifier designed for ±5-V power supply operation is described. Precision DC performance includes 100-million V/V open-loop gain, ±25-μV maximum input offset voltage, ±40-nA maximum input bias current, and 2.4-nV/√Hz (at 1 kHz) input voltage noise. AC performance includes 9-V/μs slew rate, 17-MHz bandwidth, and 1-μs settling time to 0.1%; all are measured at unity gain. The op amp is capable of directly driving into a 50-Ω load with up to ±80 mA of output drive current. A novel input bias current cancellation circuit achieves the low input bias current while maintaining a ±3.5-V minimum common-mode input voltage range. A novel output short-circuit protection circuit was developed. It provides good current limiting while allowing an output voltage swing of ±4 V. A novel input offset voltage trimming scheme using laser link cutting is introduced which consumes minimum die area while providing a ±10-μV trim solution (±3-mV trimming range) and excellent long-term stability View full abstract»

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  • A high-selectivity continuous-time GaAs balanced filter

    Publication Year: 1990 , Page(s): 889 - 892
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A second-order bandpasslike RC active filter implemented in 1-μm-gate-length GaAs technology is presented. This filter is designed to achieve low sensitivity and high selectivity at the highest possible center frequency. Its quality factor can be tuned up to 20 or 30, using low-accuracy tuning biases, while its center frequency is tuned up to 1.6 GHz View full abstract»

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  • An 8-b 1.3-MHz successive-approximation A/D converter

    Publication Year: 1990 , Page(s): 880 - 885
    Cited by:  Papers (15)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A novel successive-approximation analog-to-digital (A/D) converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 0.77 μs. The die area is 3750 mil2. This conversion technique can also be utilized in a pipelined A/D converter and enables it to achieve high speed View full abstract»

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  • Class AB CMOS amplifiers with high efficiency

    Publication Year: 1990 , Page(s): 684 - 691
    Cited by:  Papers (26)  |  Patents (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A new class AB CMOS operational-amplifier principle is presented. A transconductance amplifier based on this principle exhibits small-signal characteristics comparable to those of a conventional OTA. It has, however, a superior current efficiency and its settling time is not slew-rate limited. The new class AB principle can also be used in an output stage with a well-defined quiescent current, a rail-to-rail output swing, and a good driving capability. A two-stage amplifier with both the input and output stages based on the new principle has been realized. It features a rail-to-rail input and output common-mode range, a gain-bandwidth of 370-kHz, a settling time of less than 5 μs independent of the applied step, and a power consumption of 247 μW. It drives a resistive load of 3 kΩ in parallel with a capacitive load of 400 pF when operated on a 2.5-V/-2.5-V power supply View full abstract»

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  • Integrated mixed-mode digital-analog filter converters

    Publication Year: 1990 , Page(s): 660 - 668
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    Alternative architectures have been investigated for the integrated realization of DAFICs (digital-analog filter converters), taking into account such important design parameters as capacitance spread and total capacitor area, conversion speed and resolution, and the hardware complexity of the analog and digital parts. To demonstrate the feasibility of this novel building block, an experimental prototype algorithmic DAFIC with 8-b resolution and four FIR (finite impulse response) filtering coefficients was integrated using a 3-μm single-metal/double-poly CMOS process. Experimental results are shown to be in good agreement with the expected theoretical behavior. Preliminary work indicates that the DAFIC building block possesses significant practical advantages for the implementation of adaptive transversal structures required in baseband digital transmission applications with echo cancellation View full abstract»

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  • Programmable 2D linear filter for video applications

    Publication Year: 1990 , Page(s): 735 - 740
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm2. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm2. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan