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Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan 1991

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Displaying Results 1 - 17 of 17
  • Shifting the frequency response of switched-capacitor filters by nonuniform sampling

    Publication Year: 1991 , Page(s): 12 - 19
    Cited by:  Papers (10)  |  Patents (102)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A clock with nonuniformly spaced sampling times can be used to shift the frequency response of switched-capacitor filters. By using such a clock, which deviates only slightly from a uniform sampling clock, small shifts in the frequency response of a switched-capacitor filter can be realized. The nonuniform sampling generates undesired modulation sidebands which are small if the deviation from uniform sampling is small. Computer simulations and measured data are presented to support equations that predict the frequency response shift and the amplitude of the undesired sidebands. This technique can be used to correct frequency response errors in monolithic switched-capacitor filters caused by capacitor ratio inaccuracies. It may also be useful in applications such as spectrum analyzers and tone generators View full abstract»

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  • Cross-correlation of system outputs-ambiguity function

    Publication Year: 1991 , Page(s): 131 - 134
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Outputs of disjoint linear systems may be correlated for a nonstationary input process. For a nonstationary white input, the output cross-correlation function is simply characterized in terms of the generalized ambiguity function. An example is given for passive radiowave measurements with multiple individual sensors, in which case the ambiguity function is the spatial inverse Fourier transform of the aperture field cross-correlation View full abstract»

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  • Reduced complexity echo cancellation using orthonormal functions

    Publication Year: 1991 , Page(s): 20 - 28
    Cited by:  Papers (39)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    Top reduce the echo canceler complexity associated with the cancellations of subscriber loop echo responses with long tails, a two-stage digital echo canceler, in which the second stage is an adaptively weighted combination of orthonormal IIR responses is proposed and investigated. Satisfactory performance (70-dB cancellation) was found for a variety of loops at 80 and 320 kB symbol rates with 15 such IIR responses, based on a Laguerre functions. The first echo canceler stage is a conventional transversal filter with 20-40 tap coefficients. Substantial complexity reduction was achieved by the new structure. Adaptation convergence was also analyzed and simulated View full abstract»

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  • Neural network architecture for crossbar switch control

    Publication Year: 1991 , Page(s): 42 - 56
    Cited by:  Papers (39)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1352 KB)  

    A Hopfield neural network architecture for the real-time control of a crossbar switch for switching pockets at maximum throughput is proposed. The network performance and processing time are derived from a numerical simulation of the transitions of the neural network. A method is proposed to optimize electronic component parameters and synaptic connections, and it is fully illustrated by the computer simulation of a VLSI implementation of 4×4 neural net controller. The extension to larger size crossbars is demonstrated through the simulation of an 8×8 crossbar switch controller, where the performance of the neural computation is discussed in relation to electronic noise and inhomogeneities of network components View full abstract»

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  • High-order absolutely stable neural networks

    Publication Year: 1991 , Page(s): 57 - 65
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    The stability properties of arbitrary order continuous-time dynamic neural networks are studied in the spirit of an earlier analysis of a first-order system by M.A. Cohen and S. Grossberg (1983). The corresponding class of Lyapunov function is presented and the equilibrium points are characterized. The relationships with other continuous-time models are pointed out View full abstract»

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  • A neural net based architecture for the segmentation of mixed gray-level and binary pictures

    Publication Year: 1991 , Page(s): 66 - 77
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB)  

    A neural-net-based architecture is proposed to perform segmentation in real time for mixed gray-level and binary pictures. In this approach, the composite picture is divided into 16×16 pixel blocks, which are identified as character blocks or image blocks on the basis of a dichotomy measure computed by an adaptive 16×16 neural net. For compression purposes, each image block is further divided into 4×4 subblocks and, similar to the classical block truncation coding (BTC) scheme, a one-bit nonparametric quantizer is used to encode 16×16 character and 4×4 image blocks. In this case, however, the binary map and quantizer levels are obtained through a neural net segmentor over each block. The efficiency of the neural segmentation in terms of computational speed, data compression, and quality of the compressed picture is demonstrated. The effect of weight quantization is also discussed. VLSI implementations of such adaptive neural nets in CMOS technology are described and simulated in real time for a maximum block size of 256 pixels View full abstract»

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  • Dynamics of an adaptive hybrid

    Publication Year: 1991 , Page(s): 1 - 12
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    A bifurcation analysis is conducted of a simplified model of an adaptive hybrid using two bifurcation parameters, the adaptive stepsize and the ratio of two inputs. As these parameters vary, the system exhibits a wide variety of behaviors, including stable and unstable equilibrium points, stable and unstable periodic orbits, and aperiodic orbits. The underlying bifurcations include Hopf, flip, period-doubling sequences, and a degenerate global bifurcation which gives rise to some very complex dynamics. For inputs with a spectral density, conditions are derived under which a single stable (averaged) equilibrium exists. These results are of interest from two points of view. From the practical side, they provide an explanation of the intermittent bursting behavior of adaptive hybrids, demonstrating that bursting can be due to a slowly attractive periodic orbit (in which case the bursting eventually dies away), to a stable aperiodic orbit, or to a strange attractor (in which case the bursting persists). From the theoretical side, these results are interesting because they provide a real-world example exhibiting a rich variety of nonlinear behaviors. Due to the particular form of the model, many of these behaviors can actually be proven View full abstract»

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  • Long pipelines in single-chip digital signal processors-concepts and case study

    Publication Year: 1991 , Page(s): 100 - 108
    Cited by:  Papers (4)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    The effectiveness of long pipelines in single-chip digital signal processors for complex algorithms was studied using a processor model with 25 pipeline stages. The processor is based on a Harvard architecture. Pipelining is used to reduce the instruction cycle time compared to current signal processors. Key features of the processor model are data-stationary pipeline control, local resolution of pipeline hazards with buffering, multiple branch prediction, a mixed relative-incremental addressing scheme, and asynchronous communication between pipeline and environment. The processor is implemented as a software model. The results show that high pipeline utilization can be achieved for a variety of algorithms leading to a significantly higher performance than achieved by conventional single-chip signal processors with Harvard architecture View full abstract»

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  • Interpolation theorem for the number of generalized end-vertices of spanning trees

    Publication Year: 1991 , Page(s): 128 - 130
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The concept of end-vertex is generalized by defining the k-end-vertex, where the end-vertex of G is the 1-end-vertex of G. It is then proved that the number of k -end-vertices of spanning trees of a graph G has the interpolation property for every positive integer k. This is a generalization of S. Schuster's (1983) interpolation theorem View full abstract»

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  • The analysis and design of multidimensional FIR perfect reconstruction filter banks for arbitrary sampling lattices

    Publication Year: 1991 , Page(s): 29 - 41
    Cited by:  Papers (124)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1080 KB)  

    A general analysis of multidimensional multirate filter banks is presented. The approach is applicable to discrete signal spaces of any dimension, to multirate systems based on arbitrary downsampling and upsampling lattices, and for filter banks with any number of channels. A new numerical design procedure is also presented for multidimensional multirate perfect reconstruction filter banks, which is based on methods of nonlinearly constrained numerical optimization. An error function that depends only on the analysis filter impulse response coefficients is minimized, subject to a set of quadratic equality constraints that involve both the analysis and synthesis filter coefficients. With this design framework, it is possible to design a wide variety of filter banks that have a number of desirable properties. The analysis and synthesis filters that result are finite impulse response (FIR) and of equal size. In addition, both paraunitary and nonparaunitary filter banks can be designed with this method. Unlike paraunitary filter banks, nonparaunitary filter banks are capable of performing analysis bank functions more general than band-splitting with flat passband filters View full abstract»

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  • Clustering analyzer

    Publication Year: 1991 , Page(s): 124 - 128
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A VLSI architecture for implementing the squared-error clustering technique using extensive pipelining and parallel techniques is presented. The proposed architecture performs one pass of the squared-error algorithm, which includes finding the squared distances between every pattern and every cluster center, assigning each pattern to its closest cluster center, and recomputing the cluster centers in O(N+M+K) time units, where M is the dimension of the feature vector, N is the number of sample patterns, and K is the desired number of clusters. It needs O(N×M× K ) time units if a uniprocessor is used View full abstract»

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  • Transfinite cascades

    Publication Year: 1991 , Page(s): 78 - 85
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    Just as the natural numbers can be extended to the transfinite ordinals, so too can ladder networks and cascaded three-terminal networks be extended beyond infinity-so long as appropriate assumptions are imposed on their parameters. The author establishes the existence of such transfinite, linear or nonlinear, resistive, electrical networks. In particular, there are cascades of three-terminal networks whose nodes are sequentially numbered form the input to the output first by the natural numbers and then by transfinite ordinals all the way out to ωp, where ρ is any natural number and ω is the first transfinite ordinal. Upon specifying an appropriate source or load at the input (node 0) and also at the output (node ωp ), one obtains as a result a unique set of voltages and currents along the nodes of the cascade. This implies, in turn, that an output load far beyond infinity can be perceived by an observer at the input of the cascade. In fact, these ideas can be extended to cascades that reach still further, for example, out to ωw and beyond. All this is a natural extension of a certain kind of infinite ladder network whose load at infinity is perceptible to an observer at the input to the ladder. Such ladder networks arise in practical applications as models of various physical phenomena taking place in infinite domains View full abstract»

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  • High-quality coding of the even fields based on the odd fields of interlaced video sequences

    Publication Year: 1991 , Page(s): 140 - 142
    Cited by:  Papers (4)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    A high-quality and high-compression technique is presented for coding the even fields of digital interlaced video, assuming that the odd fields have already been coded. It may be useful in the second phase of a currently proposed scheme (MPEG) for video coding when aiming at a total bit rate of about 5 Mb/s, as well as for interlaced digital HDTV coding, including possible terrestrial and satellite all-digital transmission applications. The fields are coded with a digitally assisted hybrid multimode predictive/interpolative technique, using both predictive (hence recursive) and interpolative modes of operation. A compatible HDTV coding scheme based on the proposed technique is also outlined View full abstract»

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  • Hardware annealing in electronic neural networks

    Publication Year: 1991 , Page(s): 134 - 137
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzmann machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented View full abstract»

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  • Reduction of simultaneous-switching noise in large crossbar networks

    Publication Year: 1991 , Page(s): 86 - 99
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1244 KB)  

    Delta-I noise (simultaneous switching noise) poses a severe limitation on the size of the individual crosspoint chips that can be used to synthesize a large crossbar network. An architectural solution for reduction of the Delta-I noise in a crossbar network by using a one-sided crosspoint switching circuits is presented. Because of the existence of multiple switching paths between any pair of terminals to be connected, these circuits provide the potential for minimizing the Delta-I noise by placing the active line drivers uniformly among the switching chips. It is shown that when the sequence of connections and disconnections is arbitrary, and with a minimal nonblocking configuration of one-sided switching chips, no algorithm exists for allocation of paths in the network that can prevent the active line drivers from getting concentrated in a few chips. However, it is possible to reduce the maximum number of active line drivers in a chip by using extra columns of chips. Tight upper bounds are achieved for the number of additional columns required for a one-sided nonblocking crossbar network when a Delta-I constraint is imposed View full abstract»

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  • A VLSI-efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks

    Publication Year: 1991 , Page(s): 109 - 123
    Cited by:  Papers (33)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1456 KB)  

    A method for generating multiple arbitrarily shifted pseudorandom bit streams from a single linear feedback shift register (LFSR) is presented. Each bit stream is obtained by tapping the outputs of selected LFSR cells and feeding these tapped cell outputs through a set of exclusive-OR gates. This enables many neurons to share a single LFSR, resulting in an acceptably small overhead for VLSI implementation View full abstract»

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  • On robust eigenvalue configuration

    Publication Year: 1991 , Page(s): 138 - 139
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This study focuses on a class of disconnected subsets of the complex plane, of interest in the context of dominant pole assignment and filter design. It is first observed that the robust stability conditions originally put forth are in fact necessary and sufficient for the number of eigenvalues (matrices) or zeros (polynomials) in any given connected component to be the same for all the members of the given family. Polynomic semiguardian maps are then identified for a class of disconnected regions of interest. These maps are in fact essentially guarding with respect to one-parameter families View full abstract»

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