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IEE Proceedings - Computers and Digital Techniques

Issue 3 • Date 6 May 2005

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Displaying Results 1 - 13 of 13
  • Architecture description languages for programmable embedded systems

    Publication Year: 2005, Page(s):285 - 297
    Cited by:  Papers (14)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (439 KB)

    Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under ... View full abstract»

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  • Clockless circuits and system synthesis

    Publication Year: 2005, Page(s):298 - 316
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1726 KB)

    Future embedded systems and systems-on-chip are going to be more asynchronous than current VLSI circuits, as predicted by the International Technology Roadmap on Semiconductors. The need for CAD tools for systems without global clocking is rapidly growing. To this end, recent research has been active in two main directions, one being globally asynchronous and locally synchronous systems and the ot... View full abstract»

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  • CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip

    Publication Year: 2005, Page(s):317 - 332
    Cited by:  Papers (15)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (931 KB)

    The paper gives an overview of methods and tools that are needed to design and embed analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of these SoCs is characterised by growing design complexities and shortening time to market constraints. This requires new mixed-signal design methodologies and flows, including high-level architectural explorations and techniques ... View full abstract»

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  • Low-power RT-level synthesis techniques: a tutorial

    Publication Year: 2005, Page(s):333 - 343
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (265 KB)

    Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. While the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to below one volt and further reductions in the supply voltage begin to create more problems than a... View full abstract»

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  • Low-power system scheduling, synthesis and displays

    Publication Year: 2005, Page(s):344 - 352
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (165 KB)

    Many scheduling techniques have been presented recently which exploit dynamic voltage scaling (DVS) and dynamic power management (DPM) for both uniprocessors and distributed systems, as well as both real-time and non-real-time systems. DVS/DPM techniques have been applied not just to processors, but to interconnection networks as well. While such techniques are power-aware and aim at extending bat... View full abstract»

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  • Leakage power analysis and reduction: models, estimation and tools

    Publication Year: 2005, Page(s):353 - 368
    Cited by:  Papers (28)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (906 KB)

    The high leakage current in the nanometre regime is becoming a significant proportion of power dissipation in CMOS circuits as threshold voltage, channel length and gate oxide thickness are scaled. Consequently, the identification and estimation of different leakage currents are very important in designing low power circuits. In the paper a methodology for accurate estimation of the total leakage ... View full abstract»

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  • Hardware/software cosimulation from interface perspective

    Publication Year: 2005, Page(s):369 - 379
    Cited by:  Papers (3)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (604 KB)

    The aim is to explain the current issues of HW/SW cosimulation and to introduce a new challenge of HW/SW cosimulation for multiprocessor SoC (MPSoC). Most of the current issues are related to raising abstraction levels of HW/SW cosimulation. Mixed-level cosimulation is explained in a unified manner using a concept of 'HW/SW interface'. First, abstraction levels in HW/SW cosimulation are explained ... View full abstract»

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  • Hardware/software covalidation

    Publication Year: 2005, Page(s):380 - 392
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (325 KB)

    Hardware/software systems are embedded in devices used to enable all manner of tasks in society today. The increasing use of hardware/software systems in cost-critical and life-critical applications has led to the heightened significance of design correctness of these systems. A summary is presented of research in hardware/software covalidation. The general covalidation problem involves the verifi... View full abstract»

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  • System level validation using formal techniques

    Publication Year: 2005, Page(s):393 - 406
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (574 KB)

    Owing to increasing design complexity and intensive reuse of components, verifying the correctness of circuits and systems is becoming increasingly important. In the meantime, in many circuit design projects up to 80% of the overall design costs are caused by verification. Because of this, checking correct behaviour becomes the dominating factor. Formal verification has been proposed as a promisin... View full abstract»

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  • Exploiting defect clustering for yield and reliability prediction

    Publication Year: 2005, Page(s):407 - 413
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (250 KB)

    An integrated yield-reliability model is verified using burn-in data from 77 000 microprocessor units manufactured by IBM Microelectronics. The model is based on the fact that defects over semiconductor wafers are not randomly distributed but have a tendency to cluster. It is shown that this fact can be exploited to produce dies of varying reliability by sorting dies into bins based on how many of... View full abstract»

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  • High-resolution flash time-to-digital conversion and calibration for system-on-chip testing

    Publication Year: 2005, Page(s):415 - 426
    Cited by:  Papers (18)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (616 KB)

    Verification of timing performance in systems-on-chip (SoCs) is becoming more difficult as clock frequencies and levels of integration increase. As a result, on-chip timing measurement has become a very attractive alternative for validation of these systems because it helps to overcome the bandwidth and test access limitations inherent in SoC environments. Flash time-to-digital converters (TDCs) a... View full abstract»

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  • Low-cost modular testing and test resource partitioning for SOCs

    Publication Year: 2005, Page(s):427 - 441
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (530 KB)

    The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, long test development and test application times, and high test data volumes. A survey is presented of test resource partitioning techniques that facilitate low-cost SOC testing. Topics discussed include t... View full abstract»

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  • Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

    Publication Year: 2005, Page(s):442 - 456
    Cited by:  Papers (8)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (645 KB)

    Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. The authors propose a test flow with large multi-site testing during wafer test, enabled by a narrow SOC-ATE test interface, and relatively small multi-site testing during final (packaged-IC) test, in which all SOC pins need to be contacted. They present a throughput model for multi-site testing, v... View full abstract»

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