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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Date July 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Efficient datapath merging for partially reconfigurable architectures

    Publication Year: 2005, Page(s):969 - 980
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB) | HTML iconHTML

    Reconfigurable systems have been shown to achieve significant performance speedup through architectures that map the most time-consuming application kernel modules or inner loops to a reconfigurable datapath. As each portion of the application starts to execute, the system partially reconfigures the datapath so as to perform the corresponding computation. The reconfigurable datapath should have as... View full abstract»

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  • Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries

    Publication Year: 2005, Page(s):981 - 998
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB) | HTML iconHTML

    In this paper, we describe the algorithms used in FastImp, a program for accurate analysis of wide-band electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a precorrected fast Fourier transform (FFT) accelerated iterative method, but includes a new piecewise quadrature panel integration scheme, a new sc... View full abstract»

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  • Area-optimal technology mapping for field-programmable gate arrays based on lookup tables

    Publication Year: 2005, Page(s):999 - 1013
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB) | HTML iconHTML

    We present an exact solution to the technology mapping problem for field-programmable gate arrays (FPGAs), where the objective is to minimize the number of lookup tables (LUTs) required to map a logic circuit. The key idea is to compactly formulate the mapping problem as a mixed-integer linear-programming (MILP) problem, which can then be solved by any off-the-shelf MILP solver. MILP problem formu... View full abstract»

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  • Static leakage reduction through simultaneous Vt/Tox and state assignment

    Publication Year: 2005, Page(s):1014 - 1029
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB) | HTML iconHTML

    Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. In this paper, we propose new leakage current reduction methods in standby mode. First, we propose a combined approach of sleep-state assignment and threshold voltage (Vt) assignment in a dual-Vt process for subthreshold leakage (I... View full abstract»

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  • Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems

    Publication Year: 2005, Page(s):1030 - 1041
    Cited by:  Papers (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    While dynamic power consumption has traditionally been the primary source of power consumption, leakage power is becoming an increasingly important concern as technology feature size continues to shrink. Previous system-level approaches focus on reducing power consumption without considering leakage power consumption. To overcome this limitation, we propose a two-phase approach to combine dynamic ... View full abstract»

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  • Temperature and supply Voltage aware performance and power modeling at microarchitecture level

    Publication Year: 2005, Page(s):1042 - 1053
    Cited by:  Papers (142)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    Performance and power are two primary design issues for systems ranging from server computers to handhelds. Performance is affected by both temperature and supply voltage because of the temperature and voltage dependence of circuit delay. Furthermore, as semiconductor technology scales down, leakage power's exponential dependence on temperature and supply voltage becomes significant. Therefore, fu... View full abstract»

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  • A priori wirelength and interconnect estimation based on circuit characteristics

    Publication Year: 2005, Page(s):1054 - 1065
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the current interconnect estimation techniques estimate either the average or the total wirelength and some qualitative measure of routing demand for circuits. A priori techniques estimate these parameters without actually performing circuit placement. We propose a new a priori interconnect and ... View full abstract»

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  • Spanning graph-based nonrectilinear steiner tree algorithms

    Publication Year: 2005, Page(s):1066 - 1075
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    With advances in fabrication technology of very/ultra large scale integrated circuit (VLSI/ULSI), we must face many new challenges. One of them is the interconnect effects, which may cause longer delay and heavier crosstalk. To solve this problem, many interconnect performance optimization algorithms have been proposed. However, when these algorithms are designed based on rectilinear interconnect ... View full abstract»

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  • Early power estimation for VLSI circuits

    Publication Year: 2005, Page(s):1076 - 1088
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    Early power estimation, a requirement for design exploration early in the design phase, must often be done based on a design specification that is available only at a high level of abstraction. One way of doing this is to use high-level estimation of circuit total capacitance and average activity. This paper addresses these problems and proposes a high-level area estimation technique based on the ... View full abstract»

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  • HyPE: hybrid power estimation for IP-based systems-on-chip

    Publication Year: 2005, Page(s):1089 - 1103
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    In this paper, we present a novel power estimation scheme for programmable systems consisting of predesigned datapath and memory components. The proposed hybrid methodology yields highly accurate estimates within short runtimes by combining high-level simulation with analytical macromodeling of circuit characteristics. The kernel of our methodology is a simulation-free power estimation scheme for ... View full abstract»

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  • Layout-aware scan chain synthesis for improved path delay fault coverage

    Publication Year: 2005, Page(s):1104 - 1114
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB) | HTML iconHTML

    Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis... View full abstract»

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  • Fault diagnosis of VLSI circuits with cellular automata based pattern classifier

    Publication Year: 2005, Page(s):1115 - 1131
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB) | HTML iconHTML

    This paper reports a fault diagnosis scheme for very large scale integrated (VLSI) circuits. A special class of cellular automata (CA) referred to as multiple attractor CA (MACA) is employed for the design. State transition behavior of MACA has been analyzed to build a model that can efficiently classify the test responses of a VLSI circuit to diagnose its faulty subcircuit. The MACA-based model, ... View full abstract»

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  • Rewiring for watermarking digital circuit netlists

    Publication Year: 2005, Page(s):1132 - 1137
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    A resynthesis method to protect firm cores or circuit netlist representations is presented. The design is protected by embedding watermark by rewiring circuit with one or more redundancy addition/removal steps. This is the first known attempt to explore rewiring for watermarking. Area, performance, and testability requirements are preserved by the approach. We analyze several attack strategies and... View full abstract»

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  • On the ZBDD-based nonenumerative path delay fault coverage calculation

    Publication Year: 2005, Page(s):1137 - 1143
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    We devise one exact and one pessimistic path delay fault (PDF) grading algorithms for combinational circuits. The first algorithm, an extension to the basic grading algorithm of Padmanaban, Michael, and Tragoudas (2003), does not store all of the detected PDFs during the course of grading, and, as a further improvement, it utilizes compressed representation of PDFs. These two techniques yield a sp... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 1144
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu