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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 6 • Date June 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • GALDS: a complete framework for designing multiclock ASICs and SoCs

    Publication Year: 2005, Page(s):641 - 654
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB) | HTML iconHTML

    A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level me... View full abstract»

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  • Coding for system-on-chip networks: a unified framework

    Publication Year: 2005, Page(s):655 - 667
    Cited by:  Papers (76)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB) | HTML iconHTML

    Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this f... View full abstract»

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  • 2.5-dimensional VLSI system integration

    Publication Year: 2005, Page(s):668 - 677
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using... View full abstract»

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  • Wrapper design for multifrequency IP cores

    Publication Year: 2005, Page(s):678 - 685
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via the design of capture windows without any structural modifications to the logic within the embedded c... View full abstract»

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  • A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

    Publication Year: 2005, Page(s):686 - 695
    Cited by:  Papers (64)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (801 KB) | HTML iconHTML

    The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low sup... View full abstract»

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  • Approximate arithmetic coding for bus transition reduction in low power designs

    Publication Year: 2005, Page(s):696 - 707
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (675 KB) | HTML iconHTML

    We present a method for reducing the power consumption of compressed-code systems by selectively inverting bits that are transmitted on the bus. By incorporating bus inversion into code compression/decompression, we reduce power consumption with no cost in hardware or power relative to code compression without inversion. Inverting has to be done carefully to ensure that the codes can still be deco... View full abstract»

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  • Diagnosis of single stuck-at faults and multiple timing faults in scan chains

    Publication Year: 2005, Page(s):708 - 718
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (490 KB) | HTML iconHTML

    A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the... View full abstract»

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  • Nine-coded compression technique for testing embedded cores in SoCs

    Publication Year: 2005, Page(s):719 - 731
    Cited by:  Papers (72)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB) | HTML iconHTML

    This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume ... View full abstract»

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  • Design-for-testability and fault-tolerant techniques for FFT processors

    Publication Year: 2005, Page(s):732 - 741
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB) | HTML iconHTML

    In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, fault-tolerant approaches at the bit level and the multiply-subtract-add (MSA) modul... View full abstract»

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  • A built-in self-repair design for RAMs with 2-D redundancy

    Publication Year: 2005, Page(s):742 - 745
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves a... View full abstract»

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  • A hardware-efficient technique to implement a trellis code modulation decoder

    Publication Year: 2005, Page(s):745 - 750
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB) | HTML iconHTML

    This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a distance look-up table... View full abstract»

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  • An efficient merging scheme for prescribed skew clock routing

    Publication Year: 2005, Page(s):750 - 754
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB) | HTML iconHTML

    In ultra-deep submicron very large-scale integration (VLSI) designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power-supply noise, and tolerance to process variations. In this brief, a new merging scheme is proposed for prescribed nonzero skew routings which are useful in reducing clock cycle time, suppres... View full abstract»

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  • Comparison of high-performance VLSI adders in the energy-delay space

    Publication Year: 2005, Page(s):754 - 758
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate t... View full abstract»

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  • A novel FPGA architecture supporting wide, shallow memories

    Publication Year: 2005, Page(s):758 - 762
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB) | HTML iconHTML

    This paper investigates an architecture designed to implement wide, shallow memories on a field programmable gate array (FPGA). In the proposed architecture, existing configuration memory normally used to control the connectivity pattern of the FPGA is made user accessible. Typically, not all the switch blocks in an FPGA are used to transport signals. By adding only a modest amount of circuitry, t... View full abstract»

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  • Simultaneous V/sub t/ selection and assignment for leakage optimization

    Publication Year: 2005, Page(s):762 - 765
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    This paper presents a novel approach for leakage optimization through simultaneous V/sub t/ selection and assignment. V/sub t/ selection implies deciding the right value for V/sub t/ and assignment implies deciding which gates should be assigned a particular threshold voltage. We also include the effect of variability in threshold voltage on delay and leakage due to fabrication process variations ... View full abstract»

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  • Synthesis of Fredkin-Toffoli reversible networks

    Publication Year: 2005, Page(s):765 - 769
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. We present a method that synthesizes a network with these gates in two steps. First, our synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead.... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 770
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    Publication Year: 2005, Page(s): 771
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    Publication Year: 2005, Page(s): 772
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu