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Proceedings of the IEEE

Issue 10 • Date Oct. 1978

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Displaying Results 1 - 25 of 34
  • [Front cover and table of contents]

    Page(s): c1
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    Freely Available from IEEE
  • Scanning the issue

    Page(s): 1107 - 1108
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    Freely Available from IEEE
  • Fault-tolerance: The survival attribute of digital systems

    Page(s): 1109 - 1125
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    Fault-tolerance is the architectural attribute of a digital system that keeps the logic machine doing its specified tasks when its host, the physical system, suffers various kinds of failures of its components. A more general concept of fault-tolerance also includes human mistakes committed during software and hardware implementation and during man/machine interaction among the causes of faults that are to be tolerated by the logic machine. This paper discusses the concept of faulttolerance, the reasons for its inclusion in digital system architecture, and the methods of its implementation. A chronological view of the evolution of fault-tolerant systems and an outline of some goals for its further development conclude the presentation. View full abstract»

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  • Fault-tolerant design of local ESS processors

    Page(s): 1126 - 1145
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    The stored program control of Bell System Electronic Switching Systems (ESS) has been under development since 1953. During this period, the No. 1 ESS, the No. 2 ESS, and the No. 3 ESS have been developed and used extensively by Bell System operating companies to provide commercial telephone service. These systems serve all types of telephone offices: The large-capacity No. 1 ESS serves metropolitan offices, the medium-capacity No. 2 ESS was designed for suburban offices, and the No. 3 ESS can be found in many small rural offices. The fault tolerant design of ESS processors provides the same highly dependable telephone service established by the previous electro-mechanical systems. Pertinent processor architecture features used to achieve ESS reliablity objectives are discussed. A detailed discussion of the maintenance design of the 3A Processor is also included. View full abstract»

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  • Pluribus—An operational fault-tolerant multiprocessor

    Page(s): 1146 - 1159
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    The authors describe the Pluribus multiprocessor system, outline several techniques used to achieve fault-tolerance, describe their field experience to date, and mention some potential applications. The Pluribus system places the major responsibility for recovery from failures on the software. Failing hardware modules are removed from the system, spare modules are substituted where available, and appropriate initialization is performed. In applications where the goal is maximum availability rather than totally fault-free operation, this approach represents a considerable savings in complexity and cost over traditional implementations. The software-based reliability approach has been extended to provide enror-handling and recovery mechanisms for the system software structures as well. A number of Pluribus systems have been built and are currently in operation. Experience with these systems has given us confidence in their performance and maintainability, and leads us to suggest other applications that might benefit from this approach. View full abstract»

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  • Fault-tolerant computer system with three symmetric computers

    Page(s): 1160 - 1177
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    Many computer systems have turned increasingly to control systems, requiring more sophisticated machinery over an ever-widening range. The reliability of the system should be carefully considered in all its aspects. The concept of a control segment is introduced against local malfunctions or failures in order to save the system from going down. This paper also describes the fault tolerant control computer system with dual operation aimed at getting the fail-safe feature of the control output and complex operation features for maintenance and improvement of the system. Three "off-the-shelf" computers are connected symmetrically by three special hardwares and configuration programs not only in hardware, but also software configuration. Degradation techniques in software and hardware are introduced to prevent the system from stoppage. The actual running record shows 99.99 percent operating availability for three years in the case of the command and control system for a railway which is described here. View full abstract»

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  • A case study of C.mmp, Cm*, and C.vmp: Part I—Experiences with fault tolerance in multiprocessor systems

    Page(s): 1178 - 1199
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    Three multiprocessor systems designed, implemented, and currently operational at Carnegie-Mellon University are compared and contrasted. The design goals and architectures are summarized with a special focus on reliability features. Experiences gained in design and operation are discussed. Finally, reliability data, with a focus on transient failures, measured from each system are presented and discussed. View full abstract»

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  • A case study of C.mmp, Cm*, and C.vmp: Part II—Predicting and calibrating reliability of multiprocessor systems

    Page(s): 1200 - 1220
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    This paper focuses on measurement and modeling of hard failures in multiprocessors. The failure rate predictions of the Military Standardization Handbook 217B (MIL 217B) are compared with semiconductor chip vendor data and data from Carnegie-Mellon University's multiprocessor systems. Based on these comparisons a modified MIL 217B model is proposed. The modified model is employed to calculate module failure rates for the three multiprocessors designed, implemented, and currently operating at CMU. Hard failure reliability models for these three systems are presented. These models use the calculated module failure rates as a basis for a consistent comparison of the three systems. View full abstract»

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  • FTMP—A highly reliable fault-tolerant multiprocess for aircraft

    Page(s): 1221 - 1239
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    FTMP is a digital computer architecture which has evolved over a ten-year period in connection with several life-critical aerospace applications. Most recently it has been proposed as a fault-tolerant central computer for civil transport aircraft applications. A working emulation has been operating for some time, and the first engineering prototype is scheduled to be completed in late 1979. FTMP is designed to have a failure rate due to random causes of the order of 10-10failures per hour, on ten-hour flights where no air-borne maintenance is available. The prefered maintenance interval is of the order of hundreds of flight hours, and the probability that maintenance will be required earlier than the preferred interval is desired to be at most a few percent. The design is based on independent processor-cache memory modules and common memory modules which communicate via redundant serial buses. All information processing and transmission is conducted in triplicate so that local voters in each module can correct errors. Modules can be retired and/or reassigned in any configuration. Reconfiguration is carried out routinely from second to second to search for latent faults in the voting and reconfiguration elements. Job assignments are all made on a floating basis, so that any processor triad is eligible to execute any job step. The core software in the FFMP will handle all fault detection, diagnosis, and recovery in such a way that applications programs do not need to be involved. Failure-rate models and numerical results are described for both permanent and intermittent faults. A dispatch probability model is also presented. Experience with an experimental emulation is described. View full abstract»

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  • SIFT: Design and analysis of a fault-tolerant computer for aircraft control

    Page(s): 1240 - 1255
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    SIFT (Software Implemented Fault Tolerance) is an ultrareliable computer for critical aircraft control applications that achieves fault tolerance by the replication of tasks among processing units. The main processing units are off-the-shelf minicomputers, with standard microcomputers serving as the interface to the I/O system. Fault isolation is achieved by using a specially designed redundant bus system to interconnect the proeessing units. Error detection and analysis and system reconfiguration are performed by software. Iterative tasks are redundantly executed, and the results of each iteration are voted upon before being used. Thus, any single failure in a processing unit or bus can be tolerated with triplication of tasks, and subsequent failures can be tolerated after reconfiguration. Independent execution by separate processors means that the processors need only be loosely synchronized, and a novel fault-tolerant synchronization method is described. The SIFT software is highly structured and is formally specified using the SRI-developed SPECIAL language. The correctness of SIFT is to be proved using a hierarchy of formal models. A Markov model is used both to analyze the reliability of the system and to serve as the formal requirement for the SIFT design. Axioms are given to characterize the high-level behavior of the system, from which a correctness statement has been proved. An engineering test version of SIFT is currently being built. View full abstract»

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  • Architectures for fault-tolerant spacecraft computers

    Page(s): 1255 - 1268
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    This paper summarizes the results of a long-term research program in fault-tolerant computing for spacecraft on-board processing. In response to changing device technology this program has progressed from the design of a fault-tolerant uniprocessor to the development of fault-tolerant distributed computer systems. The unusual requirements of spacecraft computing are described along with the resulting real-time computer architectures. The following aspects of these designs are discussed: 1) architectural features to minimize complexity in the distributed computer system, 2) fault-detection and recovery, 3) techniques to enhance reliability and testability, and 4) design approaches for LSI implementation. View full abstract»

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  • Comments on "On minimal realization of transfer function matrices using Markov parameters and time moments"

    Page(s): 1274 - 1275
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    It is pointed out that the algorithm proposed in the above letter was published by the authors in 1976. Some important features of this algorithm, which have been missed in the above letter, are also described. In the above paper Shrikhande et al. have presented a method of minimal normalization based on a modified Hankel matrix containing time moments as well as Markov parameters Several comments are in order. View full abstract»

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  • Formulation of multiport equations via block matrix elimination

    Page(s): 1275 - 1277
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    Algorithms for formulating the hybrid equations of linear multiports are derived by means of block matrix elimination. The algorithms can be implemented using sparse matrix techniques. The computational requirements of each algorithm are determined, and rules on how to choose the most efficient algorithm for solving a given problem are obtained. View full abstract»

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  • An alternate method of construction of a network function from its given odd part

    Page(s): 1278
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    A new method of developing a stable network function from a specified odd part is outlined. The proposed method is based on a modification of Miyata's method of constructing a network function from a specified even part. View full abstract»

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  • A true integrable noninverting integrator with adaptive gain constant

    Page(s): 1278 - 1280
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    A circuit with a true noninverting integrator with an adaptive gain constant is described. The circuit uses a junction field effect transistor (JFET) as a voltage controlled resistor. This resistor is controlled to change the RC product of the circuit to achieve adaptivity. The adaptivity was observed over a frequency range of 1:3. The circuit is suitable for IC implementation because the performance characteristics are determined by a feedback loop, thereby making them independent of the usual tolerance in passive parameter values. View full abstract»

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  • Integrable circuit principle for synthesizing voltage-controlled nonlinear impedances

    Page(s): 1280 - 1281
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    An integrable circuit principle is described, whereby a large class of arbitrary voltage-controlled nonlinear impedances can be accurately synthesized. View full abstract»

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  • Comments on "Active RC realization of RL impedance"

    Page(s): 1280
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    It is pointed out that the configurations presented in the above letter have been previously known in the literature. View full abstract»

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  • An adaptive approach for designing phase compensation filters

    Page(s): 1281 - 1283
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    The objective of this communication is to introduce an adaptive method for designing filters to compensate for nonlinear phase shift introduced into a data stream by fixed (i.e., nonadaptive) recursive digital filters, e.g., those obtained via the bilinear transform. View full abstract»

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  • Flat magnitude low-pass filters with multiple pairs of imaginary-axis zeros

    Page(s): 1283 - 1284
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    It has been reported recently that if flatness at ω = 0 is not strictly required to be maximal, then a class of filters with one ripple near the passband edge and also a pair of imaginary-axis zeros can be generated. This correspondence extends the design further to the general case of multiple pairs of imaginary axis zeros. View full abstract»

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  • Identification of the parameters of a multicomponent signal class

    Page(s): 1284 - 1286
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    Cohn-Sfetcu et al., in the multicomponent signal analysis decaying with time, generalized a method initially used for multi-component exponential decays. This letter presents an extension of this method to multicomponent signals of different asymptotic behavior. View full abstract»

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  • Transresistance instrumentation amplifier

    Page(s): 1286 - 1287
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    A transresistance instrumentation amplifier (dual-input transresistance amplifier) was designed, and a prototype was fabricated and tested in a gamma-ray dosimeter. The circuit, explained in this letter, is a differential amplifier which is suitable for amplification of signals from current-source transducers. In the dosimeter application, the amplifier proved superior to a regular (single) transresistance amplifier, giving better temperature stability and better common-mode rejection. View full abstract»

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  • Imaging of a two-dimensional target by means of hologram matrix—An ultrasound experiment

    Page(s): 1287 - 1289
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    An experimental study is made of a two-dimension imaging system using 1-MHz ultrasound, which was suggested in a previous paper as an application of the hologram matrix concerning two orthogonal antenna arrays. Clear image reconstructions are obtained for several targets composed of a set of thin brass rods. View full abstract»

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  • Multifrequency hologram matrix and its application to a two-dimensional imaging

    Page(s): 1289 - 1290
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    The concept of a multifrequency hologram matrix is introduced and applied to a two-dimensional imaging system using a linear antenna array. The image processing is based on the coherent focusing of multifrequency beams synthesized from hologram matrices of several different frequencies. The imaging system is studied by means of a computer simulation and is shown to have a good range resolution. View full abstract»

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North Carolina State University