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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Date Mar 2005

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Displaying Results 1 - 13 of 13
  • Embedded microelectronic systems: status and trends

    Publication Year: 2005
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (47 KB)

    Advances in silicon technology and the resultant increased integration capacity are changing the way of designing integrated circuits, where the emphasis now is to design and integrate a complete system function on a single die, system-on-chip (SoC). This is unlike the traditional approach which implements a specific component function due to the limited integration capacity as an ASIC, which is t... View full abstract»

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  • Models of computation and languages for embedded system design

    Publication Year: 2005, Page(s):114 - 129
    Cited by:  Papers (16)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (405 KB)

    Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded sy... View full abstract»

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  • Analysis and optimisation of heterogeneous real-time embedded systems

    Publication Year: 2005, Page(s):130 - 147
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (730 KB)

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can hav... View full abstract»

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  • System level performance analysis - the SymTA/S approach

    Publication Year: 2005, Page(s):148 - 166
    Cited by:  Papers (112)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (534 KB)

    SymTA/S is a system-level performance and timing analysis approach based on formal scheduling analysis techniques and symbolic simulation. The tool supports heterogeneous architectures, complex task dependencies and context aware analysis. It determines system-level performance data such as end-to-end latencies, bus and processor utilisation, and worst-case scheduling scenarios. SymTA/S furthermor... View full abstract»

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  • Hardware/software partitioning of operating systems: focus on deadlock detection and avoidance

    Publication Year: 2005, Page(s):167 - 182
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (886 KB)

    As multiprocessor system-on-a-chip (MPSoC) designs become more common, hardware/software codesign engineers face new challenges involving operating system integration. To speed up operating system/MPSoC codesign, the paper presents recent research in hardware/software partitioning of a real-time operating system (RTOS). After a brief overview of the δ hardware/software RTOS design framework,... View full abstract»

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  • Modular design space exploration framework for embedded systems

    Publication Year: 2005, Page(s):183 - 192
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (445 KB)

    Design space exploration is introduced as one of the major tasks in embedded system design. After reviewing existing exploration methods at various layers of abstraction, a generic approach is described based on multi-objective decision making, black-box optimisation and randomised search strategies. The interface between problem-specific and generic parts of the exploration framework is made expl... View full abstract»

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  • Reconfigurable computing: architectures and design methods

    Publication Year: 2005, Page(s):193 - 207
    Cited by:  Papers (99)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (859 KB)

    Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. I... View full abstract»

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  • Retargetable compilers and architecture exploration for embedded processors

    Publication Year: 2005, Page(s):209 - 223
    Cited by:  Papers (3)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (732 KB)

    Retargetable compilers can generate assembly code for a variety of different target processor architectures. Owing to their use in the design of application-specific embedded processors, they bridge the gap between the traditionally separate disciplines of compiler construction and electronic design automation. In particular, they assist in architecture exploration for tailoring processors towards... View full abstract»

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  • Power aware data and memory management for dynamic applications

    Publication Year: 2005, Page(s):224 - 238
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (290 KB)

    In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy de... View full abstract»

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  • Concurrent models of computation for embedded software

    Publication Year: 2005, Page(s):239 - 250
    Cited by:  Papers (5)  |  Patents (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (198 KB)

    The prevailing abstractions for software are better suited to the traditional problem of computation, namely transformation of data, than to the problems of embedded software. These abstractions have weak notions of concurrency and the passage of time, which are key elements of embedded software. Innovations such as nesC/TinyOS (developed for programming very small programmable sensor nodes called... View full abstract»

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  • Leakage-aware compilation for VLIW architectures

    Publication Year: 2005, Page(s):251 - 260
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (402 KB)

    Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ... View full abstract»

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  • Network-on-chip architectures and design methods

    Publication Year: 2005, Page(s):261 - 272
    Cited by:  Papers (32)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (201 KB)

    Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus s... View full abstract»

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  • Asynchronous on-chip networks

    Publication Year: 2005, Page(s):273 - 283
    Cited by:  Papers (13)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (305 KB)

    Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on... View full abstract»

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