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Issue 2 • March-April 2005

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Displaying Results 1 - 13 of 13
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 2005, Page(s):2 - 3
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  • Masthead

    Publication Year: 2005, Page(s): 4
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  • Variation-tolerant design

    Publication Year: 2005, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB) | HTML iconHTML

    As we introduce this year’s Hot Chips theme issue, the frequency slowdown trend that is upon us as a result of the CMOS technology outlook has to be the single major point that stands out. It is not just the per-chip power dissipation envelope that is forcing this trend, although that factor alone is perhaps the major deterrent to frequency escalation at prior (historical) rates. View full abstract»

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  • Thinking about history and design

    Publication Year: 2005, Page(s):6 - 7
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    Freely Available from IEEE
  • Hot Chips 16: Power, Parallelism, and Memory Performance

    Publication Year: 2005, Page(s):8 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    We are pleased to introduce this special issue of IEEE Micro featuring papers that capture the best presentations from the Hot Chips 16 conference held last summer at Stanford University. View full abstract»

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  • Montecito: a dual-core, dual-thread Itanium processor

    Publication Year: 2005, Page(s):10 - 20
    Cited by:  Papers (89)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Intel's Montecito is the first Itanium processor to feature duplicate, dual-thread cores and cache hierarchies on a single die. It features a landmark 1.72 billion transistors and server-focused technologies, and it requires only 100 watts of power. Intel's Itanium 2 processor series has regularly delivered additional performance through the increased frequency and cache as evidenced by the 6-Mbyt... View full abstract»

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  • Niagara: a 32-way multithreaded Sparc processor

    Publication Year: 2005, Page(s):21 - 29
    Cited by:  Papers (394)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large amounts of on-chip parallelism to provide high throughput. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar,... View full abstract»

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  • Horus: large-scale symmetric multiprocessing for Opteron systems

    Publication Year: 2005, Page(s):30 - 40
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    Horus lets server vendors design up to 32-way Opteron systems. Horus is the only chip that targets the Opteron in an SMP implementation. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent hypertransport transaction. View full abstract»

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  • The GeForce 6800

    Publication Year: 2005, Page(s):41 - 51
    Cited by:  Papers (43)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    Graphics processing units (GPUs) continue to take on increasing computational workloads and support interactive rendering that approaches cinematic quality. The architectural drivers for GPUs are programmability, parallelism, bandwidth, and memory characteristics. This article describes how one team approached the design problem. View full abstract»

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  • Accelerating next-generation public-key cryptosystems on general-purpose CPUs

    Publication Year: 2005, Page(s):52 - 59
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    This article describes low-cost techniques for accelerating the ECC and RSA public-key cryptosystems on general-purpose processor architectures. We focus on hardware acceleration of public-key cryptosystems on 64-bit server machines. A prototype based on a Sparc CPU data path shows a clear performance advantage of ECC over RSA. View full abstract»

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  • Thread-based virtual duplex systems in embedded environments

    Publication Year: 2005, Page(s):60 - 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Virtual duplex systems provide the cost benefit of requiring only one rather than two processors. To lighten the single processor's burden and meet real-time requirements in embedded systems, the authors propose using emulated multithreading which avoids the high costs associated with traditional duplex systems without sacrificing the ability to detect and tolerate faults. View full abstract»

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  • Communications consolidation after an era of no restraints

    Publication Year: 2005, Page(s):72 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    AT&T recently accepted an offer to be acquired by another company. So did MCI, which is what is left of MCI Worldcom. Both will become part of large local telephone companies, SBC and Verizon. Qwest also would like to buy MCI, but MCI had rejected its bid, as of this writing. View full abstract»

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IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center