IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 11 • Nov 1991

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Displaying Results 1 - 13 of 13
  • Pin assignment with global routing for general cell designs

    Publication Year: 1991, Page(s):1401 - 1412
    Cited by:  Papers (26)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB)

    The author presents an algorithm which combines the pin assignment step and the global routing step in the physical design of VLSI circuits. The algorithm is based on two key theorems: the channel pin assignment theorem and the block boundary decomposition theorem. These two theorems deal successfully with the high complexity resulting from combining the pin assignment and global routing steps. Ac... View full abstract»

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  • SKOL: a system for logic synthesis and technology mapping

    Publication Year: 1991, Page(s):1342 - 1355
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    SKOL, a system for combinational logic synthesis using library of cells, with emphasis on technology mapping algorithms, is described. It combines current multilevel optimization techniques with a new approach to the technology mapping problem. This approach uses a numerical string for representing the Boolean expressions and the library cells, which allows a fast selection process. Technology map... View full abstract»

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  • A new approach to wiring layouts

    Publication Year: 1991, Page(s):1392 - 1400
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The author introduces a technique for wiring knock-knee layouts, without using two-colorable maps. This technique can be easily adapted to wire layouts on any type of grid, something that is rather complicated if one uses two-colorable maps. The author presents an algorithm for wiring a given layout in the square grid that uses at most four layers, and produces a two-layer wiring for a given layou... View full abstract»

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  • On the complexity of connectivity binding

    Publication Year: 1991, Page(s):1460 - 1465
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    The complexity of the assignment of operations to hardware components to specify the design at a register-transfer level, which is referred to as connectivity binding, is discussed. Connectivity binding is an important issue in high-level behavior synthesis systems that start with abstract behavioral descriptions and synthesize register-transfer level architectures for implementation. The correspo... View full abstract»

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  • Boundary single-layer routing with movable terminals

    Publication Year: 1991, Page(s):1382 - 1391
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    The authors study a generalization of previous results on the boundary single-layer routing (BSLR) problem. In the BSLR problem, there is a planar graph, a collection of terminals on the boundary of the infinite face, and a set of multiterminal nets. A solution of BSLR consists of a set of vertex disjoint trees interconnecting the terminals belonging to the same (multiterminal) net. An algorithm, ... View full abstract»

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  • The use of small pivot perturbation in circuit analysis

    Publication Year: 1991, Page(s):1441 - 1446
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A technique that can improve the accuracy of Gaussian elimination in those cases where small pivot magnitudes are encountered during the Gaussian elimination procedure, thus avoiding an inaccurate solution and allowing the analysis to continue, is presented. This technique is known as small pivot perturbation (SPP). It is shown that SPP can be used to provide accurate solutions in those cases wher... View full abstract»

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  • Optimal channel pin assignment

    Publication Year: 1991, Page(s):1413 - 1424
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    The authors study the channel pin assignment (CPA) problem subject to position constraints, order constraints, and separation constraints. The problem is to assign two sets of terminals to the top and the bottom of a channel to minimize channel density. It is shown that the problem is NP-hard in general and polynomial time-optimal algorithms are presented for a case where the relative orderings of... View full abstract»

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  • Analysis of digital circuits through symbolic reduction

    Publication Year: 1991, Page(s):1356 - 1371
    Cited by:  Papers (38)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1452 KB)

    The authors describe a semi-algorithmic method to extract finite-state models from an analog circuit-level model by means of homomorphic (behavior preserving) transformations. Properties to be verified are defined by ω-automata. Efficient algorithms for testing language containment of automata can then be applied to verify properties of the finite-state models. Proof of the property in the f... View full abstract»

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  • Partitioning of polynomial tasks: test generation, an example

    Publication Year: 1991, Page(s):1465 - 1468
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The circumstances under which a partitioning of a task with a polynomial complexity will result in an overall reduction of its execution time are analyzed. It is assumed that the task executor is sequential in nature, namely it can execute only one task at a time. Since partitioning of a task into smaller subtasks will, most probably, result in subtask overlap, there is a risk that a given partiti... View full abstract»

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  • FastCap: a multipole accelerated 3-D capacitance extraction program

    Publication Year: 1991, Page(s):1447 - 1459
    Cited by:  Papers (534)  |  Patents (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    A fast algorithm for computing the capacitance of a complicated three-dimensional geometry of ideal conductors in a uniform dielectric is described and its performance in the capacitance extractor FastCap is examined. The algorithm is an acceleration of the boundary-element technique for solving the integral equation associated with the multiconductor capacitance extraction problem. The authors pr... View full abstract»

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  • Channel ordering for VLSI layout with rectilinear modules

    Publication Year: 1991, Page(s):1425 - 1431
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The authors present a channel-ordering algorithm for VLSI layout with rectilinear modules. Existing approaches for layout with rectangular modules using only straight and L-shaped channels are no longer applicable. In general, rectilinear channels are needed. An important class of channels, called staircase channels, is introduced. This algorithm produces a feasible channel ordering which minimize... View full abstract»

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  • An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits

    Publication Year: 1991, Page(s):1372 - 1381
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    The probabilistic simulation approach is extended to include the computation of the variance waveform of the power/ground current, in addition to its expected waveform. The focus is on the problem of estimating the median time-to-failure (MTF) due to electromigration (EM) in the power and ground buses of CMOS circuits. Theoretical results that quantify the relationship between the MTF and the stat... View full abstract»

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  • A new preconditioner for CGS iteration in solving large sparse nonsymmetric linear equations in semiconductor device simulation

    Publication Year: 1991, Page(s):1432 - 1440
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    The authors present a new and efficient precondition method (ILUV-CGS), which is an incomplete LU (ILU) factorization by value instead of a sparse nonzero pattern, in conjunction with CGS iteration for solving nonsymmetric linear equations in finite-element simulation of semiconductor devices. To demonstrate the efficiency of this method, the simulations of a group of representative devices with d... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu