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Circuits, Devices and Systems, IEE Proceedings -

Issue 2 • Date 8 April 2005

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Displaying Results 1 - 15 of 15
  • Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizing

    Page(s): 133 - 145
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1103 KB)  

    The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the trade-off curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables. View full abstract»

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  • Linearisation of a common emitter RF amplifier using augmentation

    Page(s): 93 - 102
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1509 KB)  

    The paper describes a method of reducing nonlinear distortion in common emitter amplifiers for RF applications. Distortion reduction is achieved by the method of augmentation. A related technique has been explored in a previous paper, where it was applied to a common base amplifier. The method increases the ratio of third-order intercept to dissipated power, with no reduction in gain. Having demonstrated that the principle of base augmentation is an effective way of linearising the common base amplifier, it has been further developed in the paper to make it suitable for application to the common emitter amplifier which has a potentially wider range of uses. View full abstract»

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  • Design of an area-efficient CMOS multiple-valued current comparator circuit

    Page(s): 151 - 158
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1992 KB)  

    In the present state-of-the-art VLSI technology, the need for developing customised circuits to suit varying operating environments and specifications is escalating. The authors introduce an area-efficient current-mode comparator, which is based on modifications of the conventional CMOS current comparator. It has been verified by circuit simulations using the 0.25 μm, 0.18 μm, and 0.13 μm CMOS technology from Chartered Semiconductor Manufacturing Pte. Ltd (CHRT ) that the proposed design acts as a perfect complement to the conventional current comparator for low threshold current (Ith) levels. A low Ith is generally more favourable than a higher Ith as it tends to dissipate low static power. A more assuring and promising fact is that the area advantage becomes more significant with reducing feature size/technology. This attribute blends well with the contemporary and ongoing process technology miniaturisation. Together with the conventional and recently reported current comparator designs, the proposed current comparator has been integrated into a positive-digit adder (PDA) using the current-mode multiple-valued logic (CMMVL) approach with 1.8 V/0.18 μm CMOS technology. The PDA utilising the new current comparator occupies a silicon area of only 40.2 μm2, which is only 77.2% and 22.6% of those of the conventional and contemporary circuits, with a power-delay product improvement of 7.3% and 70.4%, respectively. View full abstract»

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  • Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching technique

    Page(s): 127 - 132
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    A novel imbalanced phase-switching technique for high-speed prescaler design is investigated. Different from the traditional 50% duty cycle phase-switching technique, it uses 1/4 duty cycle phases to increase the delay budget in dual-modulus control. It significantly improves the performance of the prescaler in terms of operating frequency and power consumption, compared with the existing 50% duty cycle phase switching technique. This improvement makes it applicable to ultra-high-speed CMOS prescaler design. Two prescalers, with 2-to-1 and 4-to-1 phase switching are designed using this technique. The proposed 2-to-1 phase switching divide-by-7/8 prescaler with simplified topology using the Chartered 0.18 micron CMOS process is capable of operating from 1.5 GHz to 6 GHz with a 7 mW power consumption from a 1.8 V supply. Such operating frequency ranges cover most of the wireless LAN standards. The prescaler with 4-to-1 phase switching can work from 2 GHz to 10 GHz with a power consumption of 15 mW from a 1.8 V supply. The proposed technique is promising in relation to multi-GHz CMOS prescaler design because it eliminates the design trade-offs associated with other techniques. View full abstract»

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  • Realising high-current gain p-n-p transistors using a novel surface accumulation layer transistor (SALTran) concept

    Page(s): 178 - 182
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (879 KB)  

    The authors report a new p-n-p surface accumulation layer transistor (SALTran) on SOI, which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional p-n-p lateral bipolar transistor (LBT) structure. From the simulation results it is observed that, depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around twenty times that of the compatible lateral bipolar transistor, without deteriorating the cutoff frequency. Reasons for the improved performance of the SALTran are discussed, based on these detailed simulation results. View full abstract»

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  • Transient dynamics in electric power system with DC transmission: fractal growth in stability boundary

    Page(s): 159 - 164
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1715 KB)  

    The paper is concerned with transient dynamics and stability of an electric power system with DC transmission. Nowadays, DC transmission systems are widely applied to conventional electric power systems. However, the transient dynamics of AC/DC power systems, affected by the active power that flows into DC transmissions, is not entirely understood. The paper derives a non-symmetrical swing equation system to analyse the transient dynamics of an AC/DC power system. The non-symmetry implies a unidirectional component of an external forcing that corresponds to both DC power and exciting power swing. The paper discusses a stability boundary and its qualitative change in the non-symmetrical swing equation system. An understanding of the stability boundary gives an important clue to the transient dynamics of AC/DC power systems. Fractal structure growth in the stability boundary caused by the change of DC power flow is described. The existence of a fractal boundary implies that the system behaviour becomes chaotic and unpredictable, depending on the operation of the DC transmission. View full abstract»

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  • Measurement-based models of a 40 Gbit/s modulator and its electrical driver for transmitter design

    Page(s): 165 - 170
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1134 KB)  

    Accurate models of the Mach-Zehnder electro-optic modulator and its electrical driver are fundamental for concurrent design of the two devices, and allow careful optimisation of the overall performance of the transmitter. Here a measurement-based 40 Gbit/s model of the two devices is proposed and an implementation using the Agilent-Advanced Design System tool is described. The 40 Gbit/s model of a Mach-Zehnder modulator has been extracted from S-parameters and DC half-wave voltage Vπ measurements. The modulator model has been used to re-design a 7 V pp travelling wave driver amplifier previously designed for a standard 50 Ω load. A model of both the original and the re-designed drivers has been extracted to check the performance of the overall transmitter. An improvement of about 6 dB has been obtained for the simulated dynamic extinction ratio with the driver re-designed by using the modulator model: a better eye-diagram is obtained at the output of the transmitter so leading to a signal more robust to attenuation and dispersion within the optical fibre. View full abstract»

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  • 0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems

    Page(s): 123 - 126
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (859 KB)  

    The authors report a 0.7 V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7 V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time compared to the conventional Manchester carry look-ahead circuit based on two-dimensional device simulation MEDICI results. View full abstract»

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  • Output buffer design for low noise and load adaptability

    Page(s): 146 - 150
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    A new output buffer design for low switching noise and load adaptability is presented. Instead of using a current source, a current limiter is proposed to reduce the switching noise and static power dissipation. Output ringing is lowered by turning off the driver stage near the end of the output transition automatically. Compared with previous designs, the proposed buffer has less switching noise and improved output ringing and speed. The proposed method is simple and effective, without the necessity for a feedback control circuit. View full abstract»

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  • Lossless vector-quantised index coding design and implementation

    Page(s): 109 - 117
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    The authors present a simple and fast online lossless compression design to encode the vector quantised indexes for 2-D still images. The computation complexity of the method is quite low and its memory requirement is small. Experimental simulations show that the proposed scheme achieves better compression efficiency than existing lossless index coding schemes. An efficient VLSI architecture for this scheme is developed and yields a processing rate of about 83.3 mega-indexes per second. The hardware architecture is implemented using an Altera FPGA chip. A demonstration system is also built by integrating the chip with an 8051 microprocessor to verify the performance of the VLSI architecture. View full abstract»

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  • All-analytic surface potential model for SOI MOSFETs

    Page(s): 183 - 188
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (957 KB)  

    An all-analytic front surface potential model for SOI MOSFETs is presented, which is not only obtained from previously developed models, but is also derived from assumptions made for approximations of various operating regions. A single formula for the drain current is obtained by smoothly connecting the analytic solutions for various operating regions. The formula can be used from accumulation to strong inversion and from the partially depleted (PD) region to the fully depleted (FD) region. Owing to the one-dimensional nature of the model, the critical gate bias at which the transition occurs between the PD and FD regions can also be obtained analytically. Most secondary effects can easily be included in the current model and the model accurately reproduces numerical and experimental results. No discontinuity in the derivative of the surface potential is found and the newly introduced parameters used in the smoothing functions do not depend strongly on the process parameters. View full abstract»

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  • Low-power single- and double-edge-triggered flip-flops for high-speed applications

    Page(s): 118 - 122
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (869 KB)  

    The paper presents new low-power flip-flops which are faster compared to previously proposed structures. The single-edge-triggered flip-flop, called the MHLFF (modified hybrid latch flip-flop), reduces the power dissipation of the HLFF (hybrid latch flip-flop) by avoiding unnecessary node transitions. To reduce the power consumption of the flip-flop further, the double-edge-triggered modified hybrid latch flip-flop (DMHLFF) is also proposed. The power consumption in the clock tree is reduced by halving the clock frequency of the MHLFF for the same throughput. In addition to the low power, the speed is higher while the area is not larger. The increase in the speed is achieved by lowering the number of the stack transistors in the discharge path. View full abstract»

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  • Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin

    Page(s): 103 - 108
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    A new approach to the design of fourth-order PLL loop filters is described. The technique allows the specification of a desired attenuation at a given offset frequency whilst maintaining the same loop natural frequency and phase margin as for a third-order loop filter. The benefit of this approach is that improved attenuation is obtained at wide frequency offsets, without compromising the in-band performance of the loop, in contrast to other approaches. Design equations are presented for this technique, its performance is confirmed by loop-gain trajectory plots and the maximum possible attenuation as a function of the design parameters is established. View full abstract»

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  • Simulation of 1×2 OTDM router employing symmetric Mach-Zehnder switches

    Page(s): 171 - 177
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (913 KB)  

    In high-speed all-optical time division multiplexed (OTDM) routers it is desirable to carry out data routing, switching, clock recovery and synchronisation in the optical domain in order to avoid the bottleneck due to optoelectronics conversion. The authors propose an optical switch based on all-optical symmetric Mach-Zehnder (SMZ) switching and investigate its characteristics. The proposed switch is to be used as a building block for a simple 1×2 OTDM router for asynchronous OTDM packet routing, where clock recovery, address recognition and payload routing are all carried out in the optical domain. Simulation and numerical results demonstrate that clock recovery, address recognition and payload routing are possible with small amounts of crosstalk. Also presented are simulation results for bit error rate (BER) performance for the 1×2 router. For a BER of 10-9 the receiver sensitivity is -26 dB compared with baseline detection without a router of -38 dB. The proposed router displays great potential for use in ultra-high-speed OTDM networks. View full abstract»

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  • Computational paradigm for nanoelectronics: self-assembled quantum dot cellular neural networks

    Page(s): 85 - 92
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1160 KB)  

    Recent work on a unique locally interconnected neuromorphic architecture that can be implemented with chemically self-assembled arrays of nanowires acting as circuit nodes is reviewed. The nanowires have non-monotonic and nonlinear current/voltage characteristics (e.g. a negative differential resistance) that provide the functionality needed for complex circuit functions. This self-assembled network, which in its most rudimentary form can be 'grown' in a beaker using traditional electrochemistry, is theoretically capable of performing Boolean logic operations, complex image processing tasks, and associative memory functions. Relevant features of the network are described, and some recent results are presented, in particular, experimental results showing that the transport nonlinearities of the nanowires can be modulated with infrared radiation. This makes it naturally amenable to optical inputs which eliminates the need for electrical input connections and contacts, thereby allowing extremely high device density. It also makes it eminently suitable for image processing tasks. Furthermore, critical features of the system are synergistic with biologically inspired networks. The relevant circuit parameters have been experimentally extracted using a prototype self-assembled structure, and they have been used in simulations to demonstrate functionality of the network for several applications. View full abstract»

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