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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2005

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Displaying Results 1 - 25 of 27
  • [Front cover]

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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  • Table of contents

    Page(s): 1209 - 1210
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  • New Associate Editor

    Page(s): 1211
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  • Device mismatch and tradeoffs in the design of analog circuits

    Page(s): 1212 - 1224
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    Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored. View full abstract»

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  • A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

    Page(s): 1225 - 1237
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    The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz fT, 0.4-μm 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 Vp-p signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class. View full abstract»

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  • High-speed high-precision CMOS analog rank order filter with O(n) complexity

    Page(s): 1238 - 1248
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    A continuous-time implementation of a voltage-mode analog rank order filter is presented. The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit. View full abstract»

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  • A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

    Page(s): 1249 - 1258
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    This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a ±0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5×1.5 mm2. View full abstract»

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  • A low-voltage folded-switching mixer in 0.18-μm CMOS

    Page(s): 1259 - 1264
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    Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-μm CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 μm×200 μm. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW. View full abstract»

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  • A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS

    Page(s): 1265 - 1277
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    This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP3 of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm2. View full abstract»

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  • A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications

    Page(s): 1278 - 1287
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    A 12-GHz monolithic silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) is presented. The receiver is based on a dual-conversion superheterodyne architecture that employs a single LO integrated in the same die. To comply with the stringent LO phase noise requirement of -101 dBc/Hz at 100 kHz offset from the carrier, an innovative VCO topology, based on a three-layer monolithic transformer, was used. The VCO exhibits a phase noise of -102 dBc/Hz at 100 kHz offset from a 5.3-GHz carrier and a 1.1-GHz tuning range. At 12 GHz, the conversion gain is 33.6 dB, the single-sideband noise figure is 5.9 dB and the output IP3 is +16 dBm. This work reports the first 12-GHz DVB-S monolithic receiver integrated in a low-cost silicon bipolar technology. View full abstract»

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  • A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

    Page(s): 1288 - 1295
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    This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-μm bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones. View full abstract»

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  • A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator

    Page(s): 1296 - 1302
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    A low voltage multiband all-pMOS VCO was fabricated in a 0.18-μm CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption. View full abstract»

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  • Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

    Page(s): 1303 - 1309
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    This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-μm CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm2 and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL. View full abstract»

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  • A 250-MHz-2-GHz wide-range delay-locked loop

    Page(s): 1310 - 1321
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    This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively. View full abstract»

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  • A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs

    Page(s): 1322 - 1330
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    An innovative burst-mode laser transmitter (BM-TX) is presented for gigabit-capable passive optical network (GPON) upstream transmission at 1.25 Gb/s. The laser bias and modulation current each can reach 80 mA with a resolution of 0.1 mA providing a total drive current up to 160 mA. Both currents are generated by 10-bit current steering digital-to-analog converters (DACs), the architecture of which is specially adapted to yield a monotonic current setting at settling times below 12.8 ns. Tests show that fast automatic power control (APC) can stabilize and track the launched optical power with a tolerance of less than 1 dB over a wide temperature range for outdoor operation. The APC only requires a straightforward calibration of the "0" and the "1" level at room temperature. Optical level monitoring on strings of four consecutive "0" bytes and two consecutive "1" bytes at 1.25 Gb/s is demonstrated. APC based on such short strings of data has not been shown before. The circuits have been designed in a 0.35 μm SiGe BiCMOS process. Experimental results show that this dc-coupled BM-TX meets the specifications of the recently approved ITU-T Recommendation G.984.2 supporting an intelligent power leveling mechanism (PLM). View full abstract»

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  • A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

    Page(s): 1331 - 1340
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    This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-μm 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330×85 μm2. View full abstract»

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  • A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder

    Page(s): 1341 - 1349
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    An integrated receiver channel of a pulsed time-of-flight (TOF) laser rangefinder for fast industrial measurement applications with the measurement accuracy of a few centimeters in the measurement range from ∼1 m to ∼30 m to noncooperative targets was developed. The receiver channel consists of a fully differential transimpedance amplifier channel, a peak detector, an rms meter and a timing discriminator. In this particular application there is no time to measure the received signal strength beforehand and it is not predictable from previous measurements, so a leading edge timing discriminator with a constant threshold voltage was used. The amplitude of the received pulse is measured with a peak detector and the amplitude information is used to compensate for the resulting walk error. The measured bandwidth of the receiver channel is 250 MHz, the maximum transimpedance 40kΩ and the input-referred noise ∼7pA/√Hz (Cphotodiode=2 pF). The timing detection accuracy of the receiver is better than ±35 mm in a single-shot measurement in a dynamic range of 1:4000 and a temperature range of 0°C to +50°C. View full abstract»

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  • A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging

    Page(s): 1350 - 1359
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    This paper presents a multiresolution general-purpose high-speed machine vision sensor with on-chip image processing capabilities. The sensor comprises an innovative multiresolution sensing area, 1536 A/D converters, and a SIMD array of 1536 bit-serial processors with corresponding memory. The sensing area consists of an area part with 1536 × 512 pixels, and a line-scan part with a set of rows with 3072 pixels each. The SIMD processor array can deliver more than 100 GOPS sustained and the on-chip pixel-analysing rate can be as high as 4Gpixels/s. The sensor is ideal for high-speed multisense imaging where, e.g., color, greyscale, internal material light scatter, and 3-D profiles are captured simultaneously. When running only 3-D laser triangulation, a data rate of more than 20 000 profiles/s can be achieved when delivering 1536 range values per profile with 8 bits of range resolution. Experimental results showing very good image characteristics and a good digital to analog noise isolation are presented. View full abstract»

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  • Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator

    Page(s): 1360 - 1365
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    The paper presents a switched-current circuit implementation of a chaotic algorithm to generate a white noise. A 3-bit digital normalizer is utilized to adjust the coefficients in the piecewise-linear transfer function such that the probability of the generated numbers will be very close to a uniform distribution. A 1.0-GHz linear track-and-hold circuit is applied in the random number generator (RNG) to achieve a wide output bandwidth. TSMC 0.25-μm one-poly five-metal CMOS process is adopted to carry out the proposed design to verify the wideband performance. When the operating clock is 10.0 MHz, the measured bandwidth of the generated noise is 4.0 MHz. View full abstract»

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  • A low-power SRAM using hierarchical bit line and local sense amplifiers

    Page(s): 1366 - 1376
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    This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to VDD/10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K×32 bits is fabricated in a 0.25-μm CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V. View full abstract»

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  • An 800-MHz embedded DRAM with a concurrent refresh mode

    Page(s): 1377 - 1387
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    An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 μs data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4× that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively. View full abstract»

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  • A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

    Page(s): 1388 - 1396
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    A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-μm CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV(pp). In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dBΩ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10-12 with a 231-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 μm×1796 μm. View full abstract»

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  • 25th International Conference on Microelectronics

    Page(s): 1399
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan