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Electron Devices, IEEE Transactions on

Issue 11 • Date Nov. 1991

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Displaying Results 1 - 25 of 31
  • Comment on "Effect of radiation and surface recombination on the characteristics of an ion-implanted GaAs MESFET

    Publication Year: 1991
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (66 KB)  

    For the original article see ibid., vol.37, no.1, p.2-10 (1990). In an attempt to investigate the effect of radiation and surface recombination on an ion implanted GaAs MESFET, S. Mishra et al., the authors of the above-titled paper, developed a closed-form analytical model of the device under illuminated condition. It is argued by the commenter that an incorrect I-V relation of the device in the illuminated condition was derived and that, therefore, the I-V relation obtained by the authors is incorrect. It is also suggested that a true I-V relation of the device in the illuminated condition can only be obtained after expressing the total charge explicitly as a function of channel voltage.<> View full abstract»

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  • On the measurement of parasitic capacitances of device with more than two external terminals using an LCR meter

    Publication Year: 1991 , Page(s): 2573 - 2575
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    A general methodology of directly measuring parasitic capacitance using an LCR meter in devices with more than two terminals is discussed. It is concluded that the accuracy of the measurement cannot be guaranteed in such devices since it is dependent on the internal structure of the device. This is demonstrated using the conventional (bulk silicon) MOSFET structure, showing that substrate or well resistance could be the dominant factor limiting measurement accuracy of parasitic capacitances, such as gate-to-drain (source), drain-to-source, and drain (source)-to substrate (well) capacitances. The authors also conclude that for the silicon-on-insulator (SOI) MOSFET structure, a direct and accurate measurement is difficult to achieve, since the measurement accuracy is impeded by the floating substrate in the structure View full abstract»

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  • Modeling of on-state MOSFET operation and derivation of maximum channel field

    Publication Year: 1991 , Page(s): 2472 - 2480
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    A novel approach to modeling MOSFET operation in the threshold region is proposed. A two-dimensional Poisson equation is solved analytically and the current continuity equation is solved iteratively in a self-consistent feedback scheme. The I-V characteristics and the profiles of channel field and mobile charge sheet are found over the entire region of device operation. The boundary between linear and saturation regions of device operation is inherently nonexistent in the model. The physical mechanism underlying the high values of maximum channel field EL beyond channel pinch-off is highlighted. A simple analytical EL model is derived. A comparison of this EL model with previous models is made in the context of the experimental data View full abstract»

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  • High-gain lateral bipolar action in a MOSFET structure

    Publication Year: 1991 , Page(s): 2487 - 2496
    Cited by:  Papers (58)  |  Patents (122)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported View full abstract»

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  • 1/f noise in GaAs filaments

    Publication Year: 1991 , Page(s): 2548 - 2553
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    A typical 1/f noise is excited in GaAs filament with the Hooge noise parameter of about αH=2×10-3 . The noise level increases in proportion to the square of the terminal voltage, and decreases approximately in inverse proportion to the total number of carriers within the device. A transition from the typical 1/f noise characteristics to the diffusion noise characteristics of MESFETs was observed when the electric field was increased above 1 kV/cm. The noise parameters were also investigated as a function of the device width between 2 and 200 μm. Deep levels within the n-GaAs active layer and the high electric field are the main factors of the nonideal 1/f characteristics View full abstract»

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  • Pre-turn-on source bipolar injection in graded NMOSTs

    Publication Year: 1991 , Page(s): 2527 - 2530
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    The influence of the pre-turn-on source bipolar injection on graded NMOST breakdown characteristics is investigated. Double-implanted As-P (n+n-) source-drain NMOS structures (DD NMOSTs) with different effective channel lengths, ranging from 1.15 to 9.15 μm, are measured. Using a simple, but accurate, semi-empirical model for the transistor operating in the breakdown region, it is shown that the DD NMOST snapback voltage is substantially decreased due to the enhanced pre-turn-on source electron emission current View full abstract»

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  • Correlation between 1/f noise and hFE long-term instability in silicon bipolar devices

    Publication Year: 1991 , Page(s): 2540 - 2547
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    Accelerated life tests with high-temperature storage and electric aging for n+-p-n silicon planar transistors were carried out. Current gain hFE increases monotonously with time during the tests, and the hFE drift is correlated with initial measured 1/f noise in the transistors, i.e. the drift amount significantly increases with the increase of noise level. The correlation coefficient of relative drift ΔhFE /hFE and 1/f noise spectral density SiB(f) is far larger than that of Δ hFE/hFE and initial DC parameters of the transistors. A quantitative theory model for the h FE drift has been developed and explains the h FE drift behavior in the tests, which suggests that the h FE drift and 1/f noise can be attributed to the same physical origin, and both are caused by the modulation of the oxide traps near the Si-SiO2 interface to Si surface recombination. 1/f noise measurement, therefore, may be used as a fast and nondestructive means to predict the long-term instability in bipolar transistors View full abstract»

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  • A three dimensional semiconductor device simulator for GaAs/AlGaAs heterojunction bipolar transistor analysis

    Publication Year: 1991 , Page(s): 2427 - 2432
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A three-dimensional semiconductor device simulator was developed to study the steady-state characteristics of heterostructure compound semiconductor devices. The semiconductor partial differential equations-Poisson's equation and the two carrier transport equations-are solved using finite-difference discretization. The Gummel iteration method and indirect space matrix solution techniques are utilized for minimizing computation time and memory requirements. This simulator was applied to the analysis of heterojunction bipolar transistors. The effect of emitter grading on the current-voltage characteristic is demonstrated. A comparison between two- and three-dimensional simulations is also presented. The results show that three-dimensional analysis is indispensable, in particular for devices of small geometry View full abstract»

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  • Planarization of emitter-base structure of heterojunction bipolar transistors by doping selective base contact and nonalloyed emitter contact

    Publication Year: 1991 , Page(s): 2423 - 2426
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The authors report an n-p-n heterojunction bipolar transistor (HBT) with a planar (and thus passivated) emitter-base structure fabricated using a simple, low-temperature technique. They use a nonalloyed emitter contact facilitated by δ-doping grown at the surface of the sample, so that the cap layer is only 75 Å thick. The base is contacted by depositing Au-Zn or Au-Be on the surface and alloying at 420°C for 10 s, resulting in an ohmic contact with the base and rectifying contact with the emitter. The authors present large-emitter area (50-μm diameter) HBTs with homogeneous-doped bases (gain of 170) and δ-doped bases (1014 cm-2, gain of 20). Upon reducing the emitter size of the latter to 3×8 μm the gain increased to 30, demonstrating excellent surface passivation View full abstract»

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  • The effects of trap-induced lifetime variations on the design and performance of high-efficiency GaAs solar cells

    Publication Year: 1991 , Page(s): 2402 - 2409
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    The authors investigate the impact of Shockley-Read-Hall (SRH) lifetime behavior directly on GaAs solar cell performance and design optimization for various lifetime-limiting defects, characterized by trap position, cross section, and trap density. It is demonstrated theoretically and experimentally, for a specific cell design, how far GaAs cell efficiency can be from the optimum efficiency if certain types of bulk defects limit the lifetime and are not properly accounted for. A realistic situation is considered where cell designers/manufacturers know the bulk lifetime at some nominal carrier concentrations but are unaware of the trap characteristics or defect responsible for this lifetime. An improved GaAs p/n heteroface cell design is proposed. This design utilizes a high-low junction and a thin base, with AlGaAs back-surface passivation View full abstract»

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  • DC I-V characteristics of field emitter triodes

    Publication Year: 1991 , Page(s): 2558 - 2562
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current IFN. Based on these observations, a simple model has been developed to calculate the I-V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from Ic=IFN-Ig as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated View full abstract»

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  • A new method for fixed oxide charge determination using a dual-gate MOS capacitor

    Publication Year: 1991 , Page(s): 2565 - 2567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A new method for fixed oxide charge determination at the silicon-silicon-dioxide interface is presented. It is based on high-frequency C-V measurements of a dual-gate MOS capacitor. Using this technique the fixed oxide charge can be accurately without knowledge of the work-function difference by means of one simple measurement. Due to its simplicity and ease of automation it can be applied to characterization and process optimization of MOS technology View full abstract»

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  • Material-based comparison for power heterojunction bipolar transistors

    Publication Year: 1991 , Page(s): 2410 - 2416
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    Various materials are studied to determine their potential in power heterojunction bipolar transistors (HBTs). The authors first start by generating an HBT figure of merit (FOM) which is defined as the product of operating frequency and output power of the HBT with 3-dB power gain. By using the FOM and available material parameters, a material-based comparison of HBT performance is done. The general tendency is for use of narrow-bandgap materials, such as Ge or InGaAs, as the base and wide-bandgap materials, such as AlGaAs, InP, SiC, or GaN, as the collector, technology permitting View full abstract»

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  • Degradation of coated impregnated cathode's surface coating

    Publication Year: 1991 , Page(s): 2554 - 2557
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    The author investigates the quantitative temperature dependence on the surface coating degradation of M-type impregnated cathodes. Osmium-ruthenium coated M-type cathodes were continuously heated at four different temperatures for 2000-20000 h in vacuum apparatus with an Auger electron spectrometer (AES). The cathode surface concentration of tungsten increases with time by diffusion from tungsten base metal. The diffusion equation is solved with the boundary condition of the insulated surface and a theoretical equation is derived which represents the tungsten surface concentration. The data calculated from this equation are in very good agreement with the measured data. The activation energy obtained for a tungsten diffusion coefficient in the surface coating (osmium-ruthenium-tungsten) is 8.4 eV. It was found that the surface coating was stable during over 100000 h at cathode temperature of 1050°CB View full abstract»

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  • Electrical and optical feedback in an InGaAs/InP light-amplifying optical switch (LAOS)

    Publication Year: 1991 , Page(s): 2452 - 2459
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A circuit model for optical and electrical feedback has been developed to investigate the cause of negative differential resistance (NDR) switching in a series connected heterojunction phototransistor (HPT) light-emitting diode (LED) device. The model considers optical feedback from the light generated in the LED, electrical feedback from the holes thermally emitted over the LED cladding layer, nonlinear gain of the HPT, the Early effect, and leakage resistance. The analysis shows that either electrical or optical feedback can be the dominant cause for the NDR, depending upon their relative strengths. The NDR observed in the devices was caused primarily by electrical feedback since the optical feedback is weak. For low input power, avalanche breakdown appears to initiate the NDR in the devices although avalanching alone cannot cause NDR View full abstract»

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  • Evaluation of 850°C wet oxide as the gate dielectric in a 0.8-μm CMOS process

    Publication Year: 1991 , Page(s): 2433 - 2441
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The authors describe a detailed comparison of a 850°C wet oxide and a 900°C dry oxide as the MOS gate dielectric in a 0.8-μm CMOS process. The device fabrication involves a GE 0.8-μm CMOS process. Emphasis is given to poly-Si gate linewidth measurements which are crucial to the interpretation of the results. The comparison of thin oxide integrity, device characteristics, hot-electron reliability, and total-dose radiation hardness between the two oxides is discussed. Specifically, it is pointed out why the PMOS punchthrough voltage requirements mandate the use of a 850°C wet oxide for the gate dielectric View full abstract»

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  • Soft-error characteristics in bipolar memory cells with small critical charge

    Publication Year: 1991 , Page(s): 2465 - 2471
    Cited by:  Papers (1)  |  Patents (95)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    The alpha-particle-induced soft-error mechanism in a high-speed bipolar static RAM (SRAM) which is used for mainframe computers is investigated using a three-dimensional (3-D) device and a circuit simulator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cell's soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an effective-charge model is proposed. This model incorporates weight coefficients that express the memory cell's soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAMs are simulated using the effective-charge model View full abstract»

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  • A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's

    Publication Year: 1991 , Page(s): 2481 - 2486
    Cited by:  Patents (71)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs View full abstract»

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  • Si-TaSi2 composite photodiodes with wavelength-independent quantum efficiency

    Publication Year: 1991 , Page(s): 2563 - 2565
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    Photodiodes have been demonstrated which utilize the grown-in Schottky junctions of Si-TaSi2 eutectic composite material to give wavelength-independent quantum efficiencies of more than 80% (corrected for reflection loss) over nearly the entire visible and near-infrared portions of the spectrum. Noise measurements show a 1/f component which produces less than 10-dB excess noise-equivalent power relative to the shot noise limit at frequencies above 800 Hz. The good quality of these devices, together with their constant quantum efficiency over a wide range of wavelength, makes them of interest for further development in many photodetector applications View full abstract»

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  • Diffusion and noise in GaAs material and devices

    Publication Year: 1991 , Page(s): 2531 - 2539
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    The variation of the diffusion coefficient D(E) versus the electric field strength E is determined at 300 K in n-type GaAs (ND=3×10-17 cm-3 ), using pulsed high-frequency noise measurements. D(E) is found to increase slightly at low field, then to decrease down to one tenth of its ohmic value near the threshold field. Long (⩾4 μm) real n+-n-n+ Gunn diodes, with an arbitrary doping profile, can be modeled. Comparisons are made, and excellent agreement is found, between experimental and theoretical characteristics of two real diodes, with notch and with gradual doping profiles. The doping profile ND(x ) is shown to have a considerable influence on the diode behavior, in regard to the electric field profile as well as the noise characteristics. Using the impedance field method, the noise current is modeled and found to by very sensitive in the D(E) variation law, in particular in the range of 2.5-4 kV/cm. The agreement between the experimental noise and the computed noise of real diodes is quite satisfactory when using the D(E) determined View full abstract»

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  • Modeling and design of interdigital structure

    Publication Year: 1991 , Page(s): 2575 - 2577
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    A computer-aided-design-compatible model is described for an interdigital structure in microstrip configuration. The interdigital structure is modeled by using the admittance matrix of the coupled microstrip lines and modified to include the discontinuities and the distributed elements. The model takes into account all the distributed effects of the structure and models them as circuit elements. The equivalent circuit elements of the interdigital structure are computed in closed-form expressions. The results are compared with other models and also with the experimental results. Even though the model does not consider the phase shift along the terminal strip, it is shown to be valid well into the gigahertz range View full abstract»

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  • Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions

    Publication Year: 1991 , Page(s): 2442 - 2451
    Cited by:  Papers (13)  |  Patents (65)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (868 KB)  

    Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent View full abstract»

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  • New scaling guidelines for MNOS nonvolatile memory devices

    Publication Year: 1991 , Page(s): 2519 - 2526
    Cited by:  Papers (9)  |  Patents (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices View full abstract»

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  • An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

    Publication Year: 1991 , Page(s): 2460 - 2464
    Cited by:  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n- and p+ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n+ and p+ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion View full abstract»

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  • An approximate analytical formulation of the intrinsic base resistance in two planar dimensions

    Publication Year: 1991 , Page(s): 2569 - 2570
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    The author demonstrates the accuracy of an approximate analytical model for the current-dependent base resistance for a two-dimensional rectangular emitter with various boundary conditions. This model is based on the analytical formulation of the one-dimensional case, with the conductance parameters empirically modified to represent two-dimensional current flow. The results of this model are compared directly to a finite-element model and the error is shown to be small for a wide range of emitter aspect ratios View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego