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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2005

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Displaying Results 1 - 25 of 36
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Changes to the Editorial Board

    Page(s): 1041
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  • Source resistance reduction of AlGaN-GaN HFETs with novel superlattice cap layer

    Page(s): 1042 - 1047
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    We have developed a novel AlGaN-GaN heterojunction field effect transistor (HFET) with an ultralow source resistance by employing the novel superlattice (SL) cap structure. The particular advantage of the SL cap, i.e., the existence of multiple layers of the polarization-induced two-dimensional electron gas (2DEG) with high mobility and high concentration at each AlGaN-GaN interface, is fully exploited for lowering the lateral resistance and the potential barrier at the interface of the SL cap and the HFET barrier layer. By designing the AlGaN-GaN thickness ratio, we have established a method to obtain the optimized SL structure and have achieved an extremely low source resistance of 0.4 Ω·mm which is lower not only than HFETs with the conventional structure but also than those with the n-GaN cap structure. The SL cap HFET fabricated on a sapphire substrate exhibited excellent dc and RF performance, i.e., maximum transconductance of over 400 mS/mm, maximum drain current of 1.2 A/mm, a cutoff frequency of 60 GHz, a maximum frequency of oscillation of 140 GHz, and a very low noise figure minimum of 0.7 dB at 12 GHz. View full abstract»

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  • Sources of transconductance collapse in III-V nitrides - consequences of velocity-field relations and source/gate design

    Page(s): 1048 - 1054
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    Experimental results from submicrometer devices in III-V nitride devices often exhibit a significant decrease in the transconductance when gate bias is increased. This creates new challenges for circuit design in III-V nitride technology. In this paper, we discuss possible sources of this collapse from a theoretical and computational standpoint. We find that polar optical phonon emission related velocity-field nonlinearities in 5-40 kV/cm region are the primary reason for the decrease in the transconductance. We also discuss possible solutions to this problem and examine the practicality of each solution. Shorter S/G spacing and higher doping in the source gate region are predicted to remove much of the transconductance collapse. View full abstract»

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  • Investigations of high-performance GaAs solar cells grown on Ge-Si1-xGex-Si substrates

    Page(s): 1055 - 1060
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    High-performance p+/n GaAs solar cells were grown and processed on compositionally graded Ge-Si1-xGex-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm2 solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm2 did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers. View full abstract»

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  • Surface recombination currents in "Type-II" NpN InP-GaAsSb-InP self-aligned DHBTs

    Page(s): 1061 - 1066
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    Surface recombination effects are studied in non-passivated non-self-aligned and self-aligned NpN InP-GaAsSb-InP double heterostructure bipolar transistors (DHBTs) down to submicrometer emitter dimensions, and over current densities ranging from 10 A/cm2 to 100 kA/cm2. The present study is motivated by the drive to scale InP DHBTs for higher speeds and integration densities. Self-aligned InP-GaAsSb-InP DHBTs are characterized by weak emitter size effects (ESEs), and periphery recombination currents are found to be very nearly identical to published results for InP-GaInAs SHBTs despite the major differences in emitter junction band alignments ("type-II" versus "type-I") and injection mechanisms (thermal versus hot electron injection). The correspondence of measured periphery currents in both systems indicates that ESEs are dominated by a mechanism common to InP-GaAsSb and InP-GaInAs devices: this requirement is fulfilled by the direct electron injection from the InP emitter mesa sidewalls onto the extrinsic base surface. Consideration of band alignments and surface depletion effects at the extrinsic base surface is used to explain the commonality of emitter size effects in InP-GaAsSb and InP-GaInAs devices. View full abstract»

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  • Visualizing the doping profile of a silicon germanium HBT with polysilicon emitter using electron holography

    Page(s): 1067 - 1071
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    Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results. View full abstract»

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  • Monte Carlo simulations of high-speed InSb-InAlSb FETs

    Page(s): 1072 - 1078
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    Self consistent Monte Carlo simulations which include impact ionization are used to study the high-speed potential of InSb field-effect transistors. It is found that the impact ionization has a strong influence on the performance of InSb for high speed. The ionization leads to a high electron drift velocity and substrate bias can be used to extract the holes which are generated in the channel. Residual hole density within the channel, however, limits the maximum speed. The substrate bias and buffer doping are critical for extracting holes from the channel without inducing excess ionization. Simulations yield a peak cutoff frequency of 820 GHz with a 0.03125-μm gate, a source to drain voltage of 0.58, and a sheet doping density of 1.7×1012 cm-2. View full abstract»

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  • Characteristics of In0.425Al0.575As-InxGa1-xAs metamorphic HEMTs with pseudomorphic and symmetrically graded channels

    Page(s): 1079 - 1086
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    In0.425Al0.575As-InxGa1-xAs metamorphic high electron mobility transistors (MHEMTs) with two different channel designs, grown by molecular beam epitaxy (MBE) system, have been successfully investigated. Comprehensive dc and high-frequency characteristics, including the extrinsic transconductance, current driving capability, device linearity, pinch-off property, gate-voltage swing, breakdown performance, unity-gain cutoff frequency, max. oscillation frequency, output power, and power gain, etc., have been characterized and compared. In addition, complete parametric information of the small-signal device model has also been extracted and discussed for the pseudomorphic channel MHEMT (PC-MHEMT) and the V-shaped symmetrically graded channel MHEMT (SGC-MHEMT), respectively. View full abstract»

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  • Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)

    Page(s): 1087 - 1096
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    The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively. View full abstract»

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  • Electronic properties of silicon nanowires

    Page(s): 1097 - 1103
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    The electronic structure and transmission coefficients of Si nanowires are calculated in a sp3d5s* model. The effect of wire thickness on the bandgap, conduction valley splitting, hole band splitting, effective masses, and transmission is demonstrated. Results from the sp3d5s* model are compared to those from a single-band effective mass model to assess the validity of the single-band effective mass model in narrow Si nanowires. The one-dimensional Brillouin zone of a Si nanowire is direct gap. The conduction band minimum can split into a quartet of energies although often two of the energies are degenerate. Conduction band valley splitting reduces the averaged mobility mass along the axis of the wire, but quantum confinement increases the transverse mass of the conduction band edge. Quantum confinement results in a large increase in the hole masses of the two highest valence bands. A single-band model performs reasonably well at calculating the effective band edges for wires as small as 1.54-nm square. A wire-substrate interface can be viewed as a heterojunction with band offsets resulting in reflection in the transmission. View full abstract»

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  • Nitride-based MQW LEDs with multiple GaN-SiN nucleation layers

    Page(s): 1104 - 1109
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    Nitride-based light emitting diodes (LEDs) separately prepared with a conventional single low-temperature (LT) GaN nucleation layer and multiple GaN-SiN nucleation layers were both prepared. It was found that we could reduce defect density and thus improve crystal quality of the GaN-based LEDs by using multiple GaN-SiN nucleation layers. With a 20-V applied reverse bias, it was found that the reverse leakage currents measured from the LED with a single LT GaN nucleation layer and the one with 10-pair GaN-SiN nucleation layers were 1.5×10-4 and 2.5×10-6 A, respectively. It was also determined that we could use the multiple GaN-SiN nucleation layers to enhance the output intensity of near ultraviolet (UV) LEDs and to improve the reliability of nitride-based LEDs. View full abstract»

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  • Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate

    Page(s): 1110 - 1115
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    In this paper, we propose a method to design charge-sensing elements for CMOS image sensor pixels on a silicon-on-sapphire (SOS) substrate. To address the low quantum efficiency problem due to very thin active film used, a backside illuminated lateral PIN photodiode on an SOS substrate is proposed and developed. It has the advantages of higher photo response with a PIN structure and improved optical transmission with a backside illumination through a transparent sapphire substrate. An active pixel sensor (APS) based on the PIN and backside illumination has been implemented in a commercially available SOS CMOS process. Acceptable sensitivity in optical conversion from the APS can be achieved, even with the ultrathin silicon film. The APS is demonstrated to function at 1.2 V, giving a dynamic range of 51 dB. View full abstract»

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  • Physical modeling and design of thin-film SOI lateral PIN photodiodes

    Page(s): 1116 - 1122
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    Lateral PIN diodes on thin-film silicon-on-insulator (SOI) substrates are photodetectors of prime interest for UV and fast IR applications. We present numerical simulations and a simple but accurate way to implement 1-D internal physical modeling of such devices. This modeling allows for the optimization of their external and macroscopic performances such as quantum efficiency and output current as a function of design parameters such as intrinsic length of the diode. Speed and dark current performances versus the intrinsic length are also addressed, and design tradeoffs are illustrated by concrete applications. For diodes with intrinsic lengths between 2 to 4 μm, our results predict quantum efficiencies of 56% to 60% at a 400-nm wavelength, with bandwidth of 1 to 10 GHz and a dark current of around 1 pA for a total diode area of 75×75 μm2 in a 0.12 μm partially depleted SOI technology. View full abstract»

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  • A novel current-scaling a-Si:H TFTs pixel electrode circuit for AM-OLEDs

    Page(s): 1123 - 1131
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    Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with a function of current scaling is proposed for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current mirror pixel electrode circuit, in this circuit a high data-to-organic light-emitting device (OLED) current ratio can be achieved, without increasing the a-Si:H TFT size, by using a cascade structure of storage capacitors. Moreover, the proposed circuit can compensate for the variations of TFT threshold voltage. Simulation results, based on a-Si:H TFT and OLED experimental data, showed that a data-to-OLED current ratio larger than 10 and a fast pixel programming time can be accomplished with the proposed circuit. View full abstract»

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  • Analysis of the parasitic S/D resistance in multiple-gate FETs

    Page(s): 1132 - 1140
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    The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node. View full abstract»

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  • Model to predict gate tunneling current of plasma oxynitrides

    Page(s): 1141 - 1147
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    Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (Jg) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO2. It is found that n-MOSFET inversion Jg is larger than p-MOSFET inversion Jg when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET Jg for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for Jg, and we estimate the nitrogen concentration required for each node and application. View full abstract»

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  • A physically based compact gate C-V model for ultrathin (EOT ∼1 nm and below) gate dielectric MOS devices

    Page(s): 1148 - 1158
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    A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schrödinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E1∝Fox23/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO2, Si3N4 and high-κ (e.g., HfO2) gate dielectrics on (100) Si with EOTs down to ∼1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance. View full abstract»

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  • On the feasibility of nanoscale triple-gate CMOS transistors

    Page(s): 1159 - 1164
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    The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations of TGFETs reveal that much more stringent body scaling for SCE control is needed for undoped bodies relative to doped ones (which are not viable for nanoscale devices) due to the suppression of corner current conduction (which is technologically advantageous) in the former. When the undoped body is scaled for adequate SCE control, further analysis shows that the generic TGFET suffers from severe layout-area inefficiency relative to the fully depleted single-gate SOI MOSFET (FDFET) and the double-gate (DG) FinFET, and the inefficiency can be improved only by evolving the TGFET into a virtual FDFET or a virtual DG FinFET. We suggest then that the TGFET is not a feasible nanoscale CMOS transistor, and thus the DG FinFET, which is more scalable than the FDFET, seems to be the most promising candidate for future CMOS applications. View full abstract»

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  • Ultrashallow junction formation by self-limiting LTP and its application to sub-65-nm node MOSFETs

    Page(s): 1165 - 1171
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    We have developed a novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way. Key technology is realized by introducing a new process combination of preamorphization implantation and a heat absorber with a phase switch layer, and by optimizing them. The Vth rolloffs of MOSFETs formed by this method were remarkably improved compared to those by rapid thermal annealing when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate complementary metal-oxide semiconductor devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit. View full abstract»

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  • Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

    Page(s): 1172 - 1179
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    We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using HfxMo(1-x) binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and HfxMo(1-x) formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness. View full abstract»

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  • Comprehensive study of drain breakdown in MOSFETs

    Page(s): 1180 - 1186
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    MOSFET breakdown voltage is strongly affected by the measurement conditions and the device layout. CDB,CGD,Rsub, and Rgate must be extracted in order to predict the device trigger voltage under subthreshold, non-dc conditions. Substrate resistance is modeled with a simple, semi-empirical equation. View full abstract»

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  • Characterization of accumulation layer capacitance for extracting data on high-κ gate dielectrics

    Page(s): 1187 - 1193
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    A new parameter extraction technique has been outlined for high-κ gate dielectrics that directly yields values of the dielectric capacitance Cdi, the accumulation layer surface potential quotient, βacc, the flat-band voltage, the surface potential φs, the dielectric voltage, the channel doping density and the interface charge density at flat-band. The parallel capacitance, Cp(=Csc+Cit), was found to be an exponential function of φs in the strong accumulation regime, for seven different high-κ gate dielectrics. The slope of the experimental lnCps) plot, i.e., |βacc|, was found to depend strongly on the physical properties of the high-κ dielectric, i.e., was inversely proportional to [(φbm*/m)12/K/Cdi], where φb is the band offset, and m* is the effective tunneling mass. Extraction of βacc represented an experimental carrier confinement index for the accumulation layer and an experimental gate-dielectric direct-tunneling current index. βacc may also be an effective tool for monitoring the effects of post-deposition annealing/processing. View full abstract»

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  • Device design guidelines for FC-SGT DRAM cells with high soft-error immunity

    Page(s): 1194 - 1199
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    This paper describes the device design guidelines for floating channel type surrounding gate transistor (FC-SGT) DRAM cells with high soft-error immunity. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional storage capacitor. The cell itself arranges the bit line (BL), storage node, and body region in a silicon pillar vertically and hence, achieves a cell area of 4F2 (F: feature size) per bit. A thin-pillar FC-SGT with a metal gate can maintain a low leakage current without using a heavy doping concentration in the body region. Furthermore, as the silicon pillar thickness is reduced, the device enters into the fully depleted operation and as a result can realize excellent switching characteristics. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor that causes soft errors to occur. However, the parasitic bipolar current can be suppressed and its duration can be shortened as the silicon pillar thickness is reduced. As a result, the amount of stored charge lost in the storage capacitor can be effectively decreased by using a thin-pillar FC-SGT. In the case of a 10-nm-thick FC-SGT, the amount lost due to the parasitic bipolar current is decreased to about 28% of that due to the leakage current. Therefore, FC-SGT DRAM is a promising candidate for future nanometer high-density DRAMs having high soft-error immunity. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology