IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 6 • June 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery

    Publication Year: 2005, Page(s):797 - 806
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active ele... View full abstract»

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  • Toffoli network synthesis with templates

    Publication Year: 2005, Page(s):807 - 817
    Cited by:  Papers (94)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB) | HTML iconHTML

    Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirecti... View full abstract»

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  • Error control schemes for on-chip communication links: the energy-reliability tradeoff

    Publication Year: 2005, Page(s):818 - 831
    Cited by:  Papers (109)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the reliability of across-chip communication. Given the reduced power budgets for SoCs, in this paper, we develop solutions for combined energy minim... View full abstract»

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  • Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing

    Publication Year: 2005, Page(s):832 - 848
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB) | HTML iconHTML

    Due to the critical role played by data memory subsystems in the performance and energy efficiency of embedded systems, the design of energy-efficient data memory architectures has received considerable attention in recent years. In this paper, we propose a novel special-purpose data memory subsystem called Xtream-Fit which is aimed at achieving high energy-delay efficiency for streaming media app... View full abstract»

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  • Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

    Publication Year: 2005, Page(s):849 - 861
    Cited by:  Papers (118)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silic... View full abstract»

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  • Efficient frequency-domain simulation technique for short-channel MOSFET

    Publication Year: 2005, Page(s):862 - 868
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB) | HTML iconHTML

    This paper proposes and investigates a short-channel MOSFET model down to a 0.1-μm regime for the frequency-domain analysis of the device operation through the harmonic balance technique. The efficiency and the preciseness of our method are validated by comparison of simulation results with the two-dimensional time-domain simulation tool, MEDICI. Along with the carrier transport model, the disp... View full abstract»

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  • Crosstalk- and performance-driven multilevel full-chip routing

    Publication Year: 2005, Page(s):869 - 878
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB) | HTML iconHTML

    In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. For performance-driven routing, we propose a novel minimum-radius minimum-cost spanning tree heuristic for global routing. Compa... View full abstract»

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  • A fast algorithm for optimal buffer insertion

    Publication Year: 2005, Page(s):879 - 891
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    The classic buffer insertion algorithm of van Ginneken has time and space complexity O(n2), where n is the number of possible buffer positions. For more than a decade, van Ginneken's algorithm has been the foundation of buffer insertion. In this paper, we present a new algorithm that computes the same optimal buffer insertion, but runs much faster. For 2-pin nets, our time complexity is... View full abstract»

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  • New data-background sequences and their industrial evaluation for word-oriented random-access memories

    Publication Year: 2005, Page(s):892 - 904
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    This paper improves upon the state of the art in the testing of intraword coupling faults (CFs) in word-oriented memories. It first presents a complete set of fault models for intraword CFs. Then, it establishes the data background sequence and tests for each intraword CF, as well as a test with complete fault coverage of the targeted faults. All introduced tests will be evaluated industrially, to... View full abstract»

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  • Optimizing program disturb fault tests using defect-based testing

    Publication Year: 2005, Page(s):905 - 915
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Nonvolatile memories (NVMs) are susceptible to a special type of faults known as program disturb faults. These faults are described using logical fault models and often functional tests are used to detect different faults that occur under such models. The use of functional fault models and tests results in the simplification of the testing process, although such tests can be very long. In this pap... View full abstract»

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  • Improving test effectiveness of scan-based BIST by scan chain partitioning

    Publication Year: 2005, Page(s):916 - 927
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    Test effectiveness of a test-per-scan built-in self-test (BIST) scheme is highly dependent on the length and number of scan chains. Fewer cycles are used to capture test responses when the length of the scan chains increases and the total number of clock cycles is fixed. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-... View full abstract»

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  • Piecewise linear model for transmission line with capacitive loading and ramp input

    Publication Year: 2005, Page(s):928 - 937
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    Transmission line effects become increasingly significant for on-chip high-speed interconnects. Efficient and accurate transmission line models are required for analysis and synthesis of such interconnects. In this paper, we first present an efficient model for the far-end response of a single transmission line considering ramp input and capacitive loading. Our model divides the time axis into a n... View full abstract»

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  • Delay analysis of CMOS gates using modified logical effort model

    Publication Year: 2005, Page(s):937 - 947
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compa... View full abstract»

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  • Combinational automatic test pattern generation for acyclic sequential circuits

    Publication Year: 2005, Page(s):948 - 956
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for th... View full abstract»

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  • Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing

    Publication Year: 2005, Page(s):956 - 965
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    Given a system-on-chip with a set of cores and a set of test resources, and the constraints on the total power consumption during test and the maximum width on the top-level test access mechanism (TAM), it is required to optimize overall testing time of the system. To solve this problem, we first generate a power-constrained test compatibility graph and then construct a set of power-constrained co... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2005, Page(s): 966
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    Publication Year: 2005, Page(s): 967
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  • IEEE Member Digital Library

    Publication Year: 2005, Page(s): 968
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu