IEEE Transactions on Computers

Issue 7 • July 2005

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Displaying Results 1 - 19 of 19
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • Editor's note

    Publication Year: 2005, Page(s):785 - 787
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  • A coarse-grain phased logic CPU

    Publication Year: 2005, Page(s):788 - 799
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1448 KB) | HTML iconHTML

    This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18μ and 0.13μ) and a five-stage p... View full abstract»

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  • XOR-based hash functions

    Publication Year: 2005, Page(s):800 - 812
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (920 KB) | HTML iconHTML

    Bank conflicts can severely reduce the bandwidth of an interleaved multibank memory and conflict misses increase the miss rate of a cache or a predictor. Both occurrences are manifestations of the same problem: objects, which should be mapped to different indices, are accidentally mapped to the same index. Suitable chosen hash functions can avoid conflicts in each of these situations by mapping th... View full abstract»

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  • A B-tree dynamic router-table design

    Publication Year: 2005, Page(s):813 - 824
    Cited by:  Papers (34)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1152 KB) | HTML iconHTML

    We propose B-tree data structures for dynamic router-tables for the cases when the filters are prefixes as well as when they are nonintersecting ranges. A crucial difference between our data structure for prefix filters and the MRT (multiway range trees) is that, in our data structure, each prefix is stored in O(1) B-tree nodes per B-tree level, whereas, in MRT, each prefix is stored in O(m) nodes... View full abstract»

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  • FPU implementations with denormalized numbers

    Publication Year: 2005, Page(s):825 - 836
    Cited by:  Papers (10)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB) | HTML iconHTML

    Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that certain designs have elected to handle them in software rather than in hardware. Traps to software can result in long execution times, which renders denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormali... View full abstract»

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  • Digit-recurrence dividers with reduced logical depth

    Publication Year: 2005, Page(s):837 - 851
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1943 KB) | HTML iconHTML Multimedia Media

    In this paper, we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient digit by introducing more concurrency and flexibility in its computation. From the proposed class of algorithms, we select one that moves part of the selection function out of the critical path, with a corresponding reduction in the critical path compared with existing alter... View full abstract»

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  • Hardware and software normal basis arithmetic for pairing-based cryptography in characteristic three

    Publication Year: 2005, Page(s):852 - 860
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (616 KB) | HTML iconHTML

    Although identity-based cryptography offers a number of functional advantages over conventional public key methods, the computational costs are significantly greater. The dominant part of this cost is the Tate pairing, which, in characteristic three, is best computed using the algorithm of Duursma and Lee. However, in hardware and constrained environments, this algorithm is unattractive since it r... View full abstract»

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  • Cantor versus Harley: optimization and analysis of explicit formulae for hyperelliptic curve cryptosystems

    Publication Year: 2005, Page(s):861 - 872
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (486 KB) | HTML iconHTML Multimedia Media

    Hyperelliptic curves (HEC) look promising for cryptographic applications, because of their short operand size compared to other public-key schemes. The operand sizes seem well suited for small processor architectures, where memory and speed are constrained. However, the group operation has been believed to be too complex and, thus, HEC have not been used in this context so far. In recent years, a ... View full abstract»

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  • An on-chip IP address lookup algorithm

    Publication Year: 2005, Page(s):873 - 885
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1256 KB) | HTML iconHTML

    This paper proposes a new data compression algorithm to store the routing table in a tree structure using very little memory. This data structure is tailored to a hardware design reference model presented in this paper. By exploiting the low memory access latency and high bandwidth of on-chip memory, high-speed packet forwarding can be achieved using this data structure. With the addition of pipel... View full abstract»

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  • An algorithm for trading off quantization error with hardware resources for MATLAB-based FPGA design

    Publication Year: 2005, Page(s):886 - 896
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1400 KB) | HTML iconHTML

    Most practical FPGA designs of digital signal processing (DSP) applications are limited to fixed-point arithmetic owing to the cost and complexity of floating-point hardware. While mapping DSP applications onto FPGAs, a DSP algorithm designer must determine the dynamic range and desired precision of input, intermediate, and output signals in a design implementation. The first step in a MATLAB-base... View full abstract»

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  • Enhancing memory-level parallelism via recovery-free value prediction

    Publication Year: 2005, Page(s):897 - 912
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2024 KB) | HTML iconHTML

    The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow memory operations such as cache misses) significantly. Therefore, for memory-intensive workloads, it becomes more important to overlap multiple cache misses than to overlap slow memory operations with other computations. In t... View full abstract»

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  • Conflict-free accesses to strided vectors on a banked cache

    Publication Year: 2005, Page(s):913 - 916
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (192 KB) | HTML iconHTML

    With the advance of integration technology, it has become feasible to implement a microprocessor, a vector unit, and a multimegabyte bank-interleaved L2 cache on a single die. Parallel access to strided vectors on the L2 cache is a major performance issue on such vector microprocessors. A major difficulty for such a parallel access is that one would like to interleave the cache on a block size bas... View full abstract»

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  • Implications of executing compression and encryption applications on general purpose processors

    Publication Year: 2005, Page(s):917 - 922
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (952 KB) | HTML iconHTML

    Compression and encryption applications are important components of modern multimedia workloads. These workloads are typically executed on application specific integrated circuits (ASICs), application specific processors (ASPs), or general purpose processors (GPPs). GPPs are flexible and allow changes in the applications and algorithms better than ASICs and ASPs. However, executing these applicati... View full abstract»

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  • Fuzzy memoization for floating-point multimedia applications

    Publication Year: 2005, Page(s):922 - 927
    Cited by:  Papers (54)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (680 KB) | HTML iconHTML

    Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances of an already executed operation. Unfortunately, this technique may not always be worth the effort due to the power consumption and area impact of the tables required to lever... View full abstract»

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  • Call for Papers for Special Issue on Nano Systems and Computing

    Publication Year: 2005, Page(s): 928
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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org