By Topic

Electrical and Computer Engineering, Canadian Journal of

Issue 1 • Date January 2003

Filter Results

Displaying Results 1 - 11 of 11
  • Canadian Journal of Electrical and Computer Engineering

    Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (134 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): 2
    Save to Project icon | Request Permissions | PDF file iconPDF (173 KB)  
    Freely Available from IEEE
  • IEEE Canada Regional Committee Members - 2002

    Page(s): c4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (125 KB)  

    Provides a listing of current committee members. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Canadian Journal of Electrical and Computer Engineering - Instructions to Authors

    Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (194 KB)  
    Freely Available from IEEE
  • A parting word

    Page(s): 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB)  

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-power single-bit full adder cells

    Page(s): 3 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (858 KB)  

    The single-bit full adder is one of the main components in almost all logic structures. The performance of logic structures is highly dependent on the adder cells. This paper discusses the performance of single-bit full adders and presents a performance analysis for those cells in CMOS technology. Fourteen single-bit full adders and three new adders, a total of different adder cells, are analyzed in terms of power and delay using 0.35, 0.25 and 0.18 µm TSMC CMOS technology. In addition, this paper discusses the charging-capability parameter of the adder cells, which represents the fan-out of each cell. The charging-capability parameter is capable of describing the performance of the adder cell in a large, as yet unbuilt structure. Hence, the performance analysis of the single-bit full adder relates the design to power, delay, and charging capability of the logic components. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of dielectric-loaded annular slot array antenna

    Page(s): 11 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (522 KB)  

    A method is established for the analysis of annular slot array antennas loaded with dielectric layers and fed by either radial waveguide or cavity. The analysis is based on the boundary value method. The Greens functions for each region are obtained, and then the induced magnetic current over the slots is expanded into Fourier series with unknown coefficients. Boundary conditions are applied, and a matrix equation for these unknown coefficients is obtained. For narrow slots the number of unknowns equals the number of annular slots, and an extremely rapid solution is obtained. The far-field formulation is derived using the magnetic current on the dielectric layer. The method is confirmed numerically by comparing the simulation results for sample small antennas with a commercial numerical tool (IE3D), and good agreement is achieved. It is shown that adding the dielectric layers can improve the antenna directivity. In comparison with other methods, the proposed method is very efficient, and its computation efforts depend on the number of annular slots and not the size of the antenna. As an example, for a single-slot antenna the number of unknowns to be determined is only one, while in IE3D it is more than 300. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • OFDM-CPM signals for wireless communications

    Page(s): 19 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB)  

    A class of orthogonal frequency division multiplexingcontinuous phase modulation (OFDM-CPM) signals is introduced in which the binary data sequence is mapped to complex symbols using the concept of correlated phase states of a CPM signal. A multiple-symbol-observation receiver is used to decode the received sequence, and an investigation of bit error rate over typical wireless multipath channels with additive white Gaussian noise is presented. The performance of a variety of OFDM-CPM signals is presented and analyzed. Performance is a function of parameter and the observation interval, both of which are at the disposal of the system designer. It is shown that OFDM-CPM is a promising signalling scheme in multipath fading channels. Results for multi- and asymmetric OFDM-CPM signals are also presented. The peak-to-average power ratio (PAPR) performance of these signals is also presented, and an algorithm to reduce PAPR is proposed that is based on a multi-amplitude CPM constellation. It is shown through numerical simulations that the proposed algorithmreduces the PAPR of a 128-carrier OFDM-CPM signal by more than 4 dB. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A pipelined architecture for ray/bezier patch intersection computation

    Page(s): 27 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB)  

    An algorithm for computing ray/B ezier patch intersections is described from a hardware design perspective. This algorithm uses patch subdivision and other geometrical techniques to find a given maximum number of intersection points nearest to the ray origin. A pipeline-based hardware architecture is proposed, the number of pipeline stages required is verified by simulation, and the performance of a load-balanced implementation based on a state-of-the-art digital signal processor is estimated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A gate duplication technique for timing optimization

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB)  

    This paper presents a timing optimization technique based on gate duplication. The relationship between gate duplication and delay reduction is first examined, and then the notion of duplication gain for selecting good candidate gates to be duplicated is introduced. The objective is to obtain maximum circuit delay reduction with the minimum number of duplications. Experiments on benchmark circuits show that this technique leads to a significant delay improvement. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of harmonic detection algorithms and their application to active power filters for harmonics compensation and resonance damping

    Page(s): 41 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB)  

    In this paper, the performance of four harmonic detection methods is evaluated in terms of accuracy, speed of convergence, computational complexity and memory requirements; operation with measurement noise and variations of the signal amplitude and fundamental frequency is considered. The harmonic detection algorithms are based on the discrete Fourier transform (DFT), the recursive discrete Fourier transform (RDFT), the Kalman filtering (KF) approach, and the instantaneous reactive power (IRP) theory. Results obtained by simulation with MATLAB/Simulink and their real-time validation with the dSPACE simulator are presented to compare the detection methods. The effectiveness of the algorithms is demonstrated in their application to the control of an active filter and a hybrid active power filter dedicated respectively to harmonics compensation and to harmonic resonance damping in industrial power systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The role of the Canadian Journal of Electrical and Computer Engineering is to provide scientific and professional activity for its members in Canada, the CJECE complements international journals and will be of particular interest to anyone involved in research and development activities in the field of electrical and computer engineering.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dr. Shahram Yousefi
Dept. of Electrical and Computer
     Engineering
Queen's University