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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2005

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Table of contents

IEEE Journal of Solid-State Circuits publication information

Table of contents

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

A study of phase noise in colpitts and LC-tank CMOS oscillators

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A single-path pulsewidth control loop with a built-in delay-locked loop

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

Design techniques for single-low-V_DD CMOS systems

Design analysis and circuit enhancements for high-speed bipolar flip-flops

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS

A 1.25-gb/s burst-mode receiver for GPON applications

A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

A 400-MHz random-cycle dual-port interleaved DRAM (D²RAM) with standard CMOS Process

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2005

IEEE Journal of Solid-State Circuits information for authors

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