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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • Date May 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Guest Editorial

    Publication Year: 2005, Page(s):661 - 662
    Cited by:  Papers (2)
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  • Throughput-driven floorplanning with wire pipelining

    Publication Year: 2005, Page(s):663 - 675
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB) | HTML iconHTML

    The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the pr... View full abstract»

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  • Early-stage power grid analysis for uncertain working modes

    Publication Year: 2005, Page(s):676 - 682
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB) | HTML iconHTML

    High-performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designe... View full abstract»

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  • Congestion-aware topology optimization of structured power/ground networks

    Publication Year: 2005, Page(s):683 - 695
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB) | HTML iconHTML

    This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connected to each other enables the use of a hierarchical circuit analysis approach to identify the tiles co... View full abstract»

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  • A predictive distributed congestion metric with application to technology mapping

    Publication Year: 2005, Page(s):696 - 710
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB) | HTML iconHTML

    Due to increasing design complexities, routing congestion has become a critical problem in very large scale integration designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization. Our technology mapping algorithms are guided by a probabilistic congestion map for the subject graph to identify the co... View full abstract»

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  • Sensitivity guided net weighting for placement-driven synthesis

    Publication Year: 2005, Page(s):711 - 721
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    Net weighting is a key technique in timing-driven placement (TDP), which plays a crucial role for deep submicron very large scale integration of physical synthesis and timing closure. A popular way to assign net weight is based on its slack, such that the worst negative slack (WNS) of the entire circuit may be minimized. While WNS is an important optimization metric, another figure of merit (FOM),... View full abstract»

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  • FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model

    Publication Year: 2005, Page(s):722 - 733
    Cited by:  Papers (58)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB) | HTML iconHTML

    In this paper, we present FastPlace-a fast, iterative, flat placement algorithm for large-scale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be solved efficiently by some analytical techniques. However it suffers from some drawbacks. First, the resulting pl... View full abstract»

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  • Implementation and extensibility of an analytic placer

    Publication Year: 2005, Page(s):734 - 747
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1424 KB) | HTML iconHTML

    Automated cell placement is a critical problem in very large scale integration (VLSI) physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia and industry. A novel and simple objective function for spreading cells over the placement area is described in the patent of Naylor et al. (U.S. Pat.... View full abstract»

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  • Mixed block placement via fractional cut recursive bisection

    Publication Year: 2005, Page(s):748 - 761
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB) | HTML iconHTML

    Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scalability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifi... View full abstract»

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  • A study of netlist structure and placement efficiency

    Publication Year: 2005, Page(s):762 - 772
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB) | HTML iconHTML

    In this paper, we examine the relationship between netlist structure and the efficiency of placers measured in terms of quality and stability of results. We analyze three types of placers: analytic, simulated-annealing based, and partition based. We have tested these placers on industrial and synthetic benchmarks. Based on our observations and analyzes of experimental results, we draw several usef... View full abstract»

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  • General skew constrained clock network sizing based on sequential linear programming

    Publication Year: 2005, Page(s):773 - 782
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB) | HTML iconHTML

    We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivitie... View full abstract»

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  • An improved long distance treatment for mutual inductance

    Publication Year: 2005, Page(s):783 - 793
    Cited by:  Papers (5)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    This paper examines the controversy between two approaches to inductance extraction: loop versus partial treatments for integrated circuit applications. We advocate the first one, and explicitly show that the alternative demands monopole-like magnetic configurations as well as dense inductance matrices. We argue that the uncertainties in the loop inductance treatment associated with possibly unkno... View full abstract»

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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 794
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  • Call for papers on Ninth IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2005)

    Publication Year: 2005, Page(s): 795
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  • Explore IEL IEEE's most comprehensive resource

    Publication Year: 2005, Page(s): 796
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu