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IEE Proceedings E - Computers and Digital Techniques

Issue 5 • Date Sep 1991

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Displaying Results 1 - 13 of 13
  • Analysis of branch handling strategies under hierarchical memory system

    Publication Year: 1991, Page(s):319 - 328
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (620 KB)

    Branch instructions form a significant fraction of executed instructions in a computer program, and handling them is thus a crucial design issue for any architecture. In a hierarchical memory system, branch handling not only causes the pipeline drain but also results in more instructions being executed, which can result in a higher miss ratio. These phenomena are relevant to the resolution of the ... View full abstract»

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  • Design and testing of easily testable PLA

    Publication Year: 1991, Page(s):357 - 360
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (284 KB)

    A technique for designing and testing of an easily testable programmable logic array (PLA) is proposed in which the test vectors are derivable directly from the personality matrix of the PLA by simple algorithms. This technique requires few test vectors for testing. The test evaluation is simple, because in the fault-free condition, the output patterns for some of the test vectors are the same as ... View full abstract»

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  • SWIFT: stack-based microprocessor for LISP and PROLOG

    Publication Year: 1991, Page(s):299 - 304
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    SWIFT is a stack-based microprocessor designed for the efficient execution of LISP and PROLOG. The paper describes the architecture of a VLSI implementation of SWIFT which gives more than 1 Mlips performance, yet only requires 16K gates. The processor was designed at a high level in ELLA and was synthesised to the gate level using LOCAM. View full abstract»

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  • Colour image segmentation by clustering

    Publication Year: 1991, Page(s):368 - 376
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (480 KB)

    A new clustering technique is described for segmenting the colour images of natural scenes. The proposed method detects image clusters in some linear decision volumes of the (L*, a*, b*) uniform colour space. The detected clusters are projected onto the line of the Fisher discriminant for 1-D thresholding. This permits the use of all the property values of colour clusters and, in turn, produces be... View full abstract»

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  • Design and VLSI implementation of mod-127 multiplier using cellular automaton-based data compression techniques

    Publication Year: 1991, Page(s):351 - 356
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (404 KB)

    A new technique for the design and VLSI implementation of a mod-127 multiplier based on two-dimensional cellular automata (CA) is presented using two-micrometre CMOS design rules. This technique uses the data compression capabilities of CA, which arise due to the availability of symmetrical global states, to reduce the silicon area required for these modulo arithmetic units by about 90%. The reduc... View full abstract»

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  • VLSI design of inverse-free Berlekamp-Massey algorithm

    Publication Year: 1991, Page(s):295 - 298
    Cited by:  Papers (54)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (188 KB)

    The Berlekamp-Massey iterative algorithm for decoding BCH codes is modified to eliminate the calculation of inverses. This new algorithm is useful in the practical application of multiple-error-correcting BCH or RS codes. A VLSI architecture is developed for this algorithm. View full abstract»

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  • Synchronisation in parallel processing of finite sequences

    Publication Year: 1991, Page(s):329 - 334
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (336 KB)

    A parallel processing environment where jobs arrive in the form of finite sequences of tasks is considered. Service is provided by multiple parallel servers, so that tasks belonging to a job must be resequenced before leaving the system. A queueing and delay analysis of the system is performed allowing performance measures to be obtained concerning the effects of synchronisation on the behaviour o... View full abstract»

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  • Systolic realisation for 2-D convolution using configurable functional method in VLSI parallel array designs

    Publication Year: 1991, Page(s):361 - 367
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (368 KB)

    Besides introduction to the configurable functional method (CFM) proposed by the first author, which achieves high configurability to match various application aspects, a new realisation of 2-D convolution is presented using the CFM. It has the advantage of CFM arrays whose PEs and array are configurable. In systolic realisation of 2-D convolution with window size on a mesh-connected 2-D CFM array... View full abstract»

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  • Parsing instruction set computers

    Publication Year: 1991, Page(s):305 - 312
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    A class of processors is introduced with instruction sets that are specialised for parsing. The types of instructions required to parse regular expressions and context free grammars are identified. Possible implementations of parser instruction set computers in the implementation of transducers are discussed. Two experimental parsing instruction set computers intended for text retrieval are descri... View full abstract»

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  • New parallel Hough transform for circles

    Publication Year: 1991, Page(s):335 - 344
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (792 KB)

    The Hough transform is a well known medium-level image recognition technique for the detection of curves. The conventional Hough technique requires a three-dimensional accumulator array for the detection of circles. A new scheme which uses only a pair of two-dimensional accumulator arrays to reduce the storage and computation time by an order of magnitude or more is proposed. This new scheme is ca... View full abstract»

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  • Heuristic model for task allocation in distributed computer systems

    Publication Year: 1991, Page(s):313 - 318
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (400 KB)

    In distributed computing systems, partitioning of application software into modules and proper allocation of modules among processors are important factors for efficient utilisation of resources. A method for static allocation of modules to processors, with the constraints of minimising interprocessor communication cost and load balancing is presented. The heuristic approach forms module clusters ... View full abstract»

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  • Performance analysis of dynamic multitasking imprecise computation system

    Publication Year: 1991, Page(s):345 - 350
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (372 KB)

    The scheduling of tasks in dynamic multitasking computer systems using imprecise partial computations is studied. In this system, tasks arrive randomly during run-time, and they are to be processed as quickly as possible. The task is modelled in such a way that each task has two parts of computation: a mandatory part, and an optional part. The tasks are scheduled such that: if the total number of ... View full abstract»

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  • Tagged systolic arrays

    Publication Year: 1991, Page(s):289 - 294
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (324 KB)

    Design of systolic arrays from a set of nonlinear and nonuniform recurrence equations is discussed. A systematic method for deriving a systolic design in such cases is presented. A novel architectural idea, termed a tagged systolic array, is introduced. The design methodology described broadens the class of algorithms amenable for tagged systolic array implementation. The methodology is illustrate... View full abstract»

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