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Design & Test of Computers, IEEE

Issue 2 • Date March-April 2005

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Displaying Results 1 - 19 of 19
  • [Front cover]

    Publication Year: 2005 , Page(s): c1
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  • FPGA-enabled computing architectures

    Publication Year: 2005 , Page(s): 81
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  • Table of contents

    Publication Year: 2005 , Page(s): 82 - 83
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  • Masthead

    Publication Year: 2005 , Page(s): 84
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  • Guest Editors' Introduction: Advances in Configurable Computing

    Publication Year: 2005 , Page(s): 85 - 89
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (73 KB) |  | HTML iconHTML  

    At times, it appears that the many definitions of configurable computing are every bit as configurable as the technology itself. For example, Wikipedia-the free, online, user-editable encyclopedia-defines configurable computing (or, synonymously, reconfigurable computing) as ".... computer processing with highly flexible computing fabrics. The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the data path itself in addition to the control flow' (http://en.wikipedia.org/wiki/Configurable_computing). View full abstract»

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  • Architecture exploration for a reconfigurable architecture template

    Publication Year: 2005 , Page(s): 90 - 101
    Cited by:  Papers (66)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    Coarse-grained architectures (CGRAs) can be tailored and optimized for different application domains. The vast design space of coarse-grained reconfigurable architectures complicates the design of optimized processors. The goal is to design a domain-specific processor that provides just enough-flexibility for that domain while minimizing the energy consumption for a given level of performance. However, a flexible architecture template and a retargetable simulator and compiler enable systematic architecture exploration that can lead to more efficient domain-specific architecture design. This article presents such an environment and an architecture exploration for a novel CGRA template. View full abstract»

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  • Seamless hardware-software integration in reconfigurable computing systems

    Publication Year: 2005 , Page(s): 102 - 113
    Cited by:  Papers (22)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    Ideally, reconfigurable-system programmers and designers should code algorithms and write hardware accelerators independently of the underlying platform. To realize this scenario, the authors propose a portable, hardware-agnostic programming paradigm, which delegates platform-specific tasks to a system-level virtualization layer. This layer supports a chosen programming model and hides platform details from users much as general-purpose computers do. We introduce multithreaded programming model for reconfigurable computing based on a unified virtual-memory image for both software and hardware application parts. We also address the challenge of achieving seamless hardware-software interfacing and portability with minimal performance penalties. View full abstract»

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  • BEE2: a high-end reconfigurable computing system

    Publication Year: 2005 , Page(s): 114 - 125
    Cited by:  Papers (77)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    The Berkeley Emulation Engine 2 (BEE2) project is developing a reusable, modular, and scalable framework for designing high-end reconfigurable computers, including a processing-module building block and several programming models. Using these elements, BEE2 can provide over 10 times more computing throughput than a DSP-based system with similar power consumption and cost and over 100 times that of a microprocessor-based system. View full abstract»

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  • Test solution selection using multiple-objective decision models and analyses

    Publication Year: 2005 , Page(s): 126 - 134
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    Designing new automatic test equipment (ATE) frameworks in alignment with the advances in semiconductor technology remains one of the most difficult challenges in the test community. This article presents an elegant methodology for analyzing different models for ATE operation. The methodology ultimately provides a single figure of merit for evaluation and comparison. View full abstract»

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  • Scalable processor instruction set extension

    Publication Year: 2005 , Page(s): 136 - 148
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Coarse-grained reconfigurable platforms are good for parallel data-intensive applications but inefficient for sequential control-dominated code. This article explores the integration of the general purpose Sparc-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. The integration's goal is to optimize the execution of complex multimedia applications such as MPEG-4. View full abstract»

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  • B#: a battery emulator and power-profiling instrument

    Publication Year: 2005 , Page(s): 150 - 159
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1600 KB) |  | HTML iconHTML  

    B# (B sharp) is a programmable power supply that emulates battery behavior. It measures current load, calls a battery simulation program to compute voltage in real time, and controls a linear regulator to mimic a battery's voltage output. The instrument enables validation of battery-aware power optimization techniques with accurate controllable reproducible results. View full abstract»

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  • Using a periodic square wave test signal to detect crosstalk faults

    Publication Year: 2005 , Page(s): 160 - 169
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    Built-in self test (BIST) scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. The scheme tests for crosstalk faults with a periodic square wave test signal under applied random patterns generated by a linear feedback shift register (LFSR), which is transconfigured from the embedded circuit's boundary scan cells. The scheme simplifies test generation and test application while obviating the fault occurrence timing issue. Experimental results show that coverage for the induced-glitch type of crosstalk fault for large benchmark circuits can easily exceed 90%. View full abstract»

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  • Driving the $5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel

    Publication Year: 2005 , Page(s): 170 - 180
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    Ken Wagner, IEEE Design & Test's interviews editor, spoke with Intel's Digital Enterprise Group Senior Vice President and General Manager Pat Gelsinger in a wide-ranging interview discussing Intel's R&D initiatives including its wireless strategy, business models, and plans for technologies in other areas, such as precision biology. D&T also charts Pat's extraordinary career at Intel. At the time of the interview, Pat was the first-ever chief technology officer for Intel, managing the majority of the research labs for the company. Since the time of the interview, he has moved to manage the Digital Enterprise Group, the largest business group in the company owning products sold to business and communications customers. View full abstract»

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  • Sharing standards work with Japan

    Publication Year: 2005 , Page(s): 182 - 183
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    The IEEE is an international body, and its standards are likewise international in scope. However, in many areas such as EDA, the major locus of development work is in the US, and more specifically, in Silicon Valley. It is very easy to take the path of least resistance and hold standards meetings in San Jose, California, where attendance is generally good because many participants live within a few miles. Unfortunately, this path can lead to a myopic view of user needs and frustrate interested people from other regions. The Design Automation Standards Committee (DASC; http://www.dasc.org) of the IEEE Computer Society has a long history of rotating its meetings to other areas, including Europe and Asia, to avoid this problem. View full abstract»

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  • The network is the chip

    Publication Year: 2005 , Page(s): 184 - 185
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  • ITC 2004 panels: Part 1

    Publication Year: 2005 , Page(s): 186 - 189
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    Panel sessopms have long been part of the International Test Conference technical program; theyprovide an informal and entertaining opportunity for energetic ITC audiences to discuss and debate a wide range of subjects with industry and research experts. The ITC 2004 panels continued this tradition with an intriguing slate of panel sessions that educated the community and built interest in emerging issues while providing controversy and fun at the same time. View full abstract»

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  • DATC Newsletter

    Publication Year: 2005 , Page(s): 190
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  • IEEE Computer Society Information

    Publication Year: 2005 , Page(s): 191
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  • Déjà vu, all over again

    Publication Year: 2005 , Page(s): 192
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    If you work in the same technical field long enough, you start to see history repeat itself: The more things change, the more they stay the same. View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty