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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • April 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s):c1 - 501
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing

    Publication Year: 2005, Page(s):502 - 515
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    As process geometries shrink, leakage currents and charge sharing are becoming increasingly critical problems, especially in full-custom circuit designs. Excessive leakage or charge sharing may cause functional failure at some or all operating conditions. Traditional circuit-analysis techniques may be used to verify if leakage currents are within allowable limits so as not to cause functional fail... View full abstract»

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  • Context sensitive symbolic pointer analysis

    Publication Year: 2005, Page(s):516 - 531
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB) | HTML iconHTML

    One of the bottlenecks in the recent movement of hardware synthesis from behavioral C programs is the difficulty in reasoning about runtime pointer values at compile time. The pointer analysis problem has been investigated in the compiler community for two decades and has yielded efficient, polynomial time algorithms for context-insensitive (CI) analysis. However, at the accuracy level for which h... View full abstract»

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  • Early evaluation for performance enhancement in phased logic

    Publication Year: 2005, Page(s):532 - 550
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB) | HTML iconHTML

    Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function... View full abstract»

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  • Energy- and performance-aware mapping for regular NoC architectures

    Publication Year: 2005, Page(s):551 - 562
    Cited by:  Papers (272)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (803 KB) | HTML iconHTML

    In this paper, we present an algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. At the same time, the performance of the resulting communication system is guaranteed to satisfy the specified design constr... View full abstract»

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  • Layout verification for mixed-domain integrated MEMS

    Publication Year: 2005, Page(s):563 - 577
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1848 KB) | HTML iconHTML

    As design of integrated microelectromechanical systems (MEMS) mature, there is an increasing need for verification tools for such mixed-domain layouts. This requires a mixed-domain layout-versus-schematic tool capable of extracting an integrated schematic from the mixed-domain layout and verifying it against the design schematic. This paper reports on a prototype implementation of such a tool and ... View full abstract»

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  • Simultaneous power supply planning and noise avoidance in floorplan design

    Publication Year: 2005, Page(s):578 - 587
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    With today's advanced integrated circuit manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single system on a chip. However, without careful power supply planning in layout, the design of chips will suffer from local hot spots, insufficient power supply, and signal integrity problems. Postfloorplanning or postroute methodologies in solvin... View full abstract»

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  • The Y architecture for on-chip interconnect: analysis and methodology

    Publication Year: 2005, Page(s):588 - 599
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    The Y architecture for on-chip interconnect is based on pervasive use of 0°, 120°, and 240° oriented semiglobal and global wiring. Its use of three uniform directions exploits on-chip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives in-depth analysis of deployment issues associated with the Y architecture. Our contributions are as foll... View full abstract»

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  • An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations

    Publication Year: 2005, Page(s):600 - 608
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    In this paper, we propose a fast algorithm to construct a performance-driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently, several algorithms have been published addressing the routing tree construction problem. However, all these algorithms are slow and not scalable. In this paper, we propose an algorithm which is fast and ... View full abstract»

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  • Buffer planning as an Integral part of floorplanning with consideration of routing congestion

    Publication Year: 2005, Page(s):609 - 621
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1086 KB) | HTML iconHTML

    The dominating contribution of interconnect to system performance has made it critical to plan the resources of the buffers and routes in the early stage of the layout. In this paper, we integrate floorplanning with buffer insertion for performance-driven design processes. We devise a two-step method to evaluate the feasible buffer insertion sites, which can improve the efficiency of the buffer-pl... View full abstract»

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  • Finite memory test response compactors for embedded test applications

    Publication Year: 2005, Page(s):622 - 634
    Cited by:  Papers (50)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB) | HTML iconHTML

    This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100×, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. Th... View full abstract»

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  • A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip

    Publication Year: 2005, Page(s):635 - 645
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    This paper deals with a significant problem affecting embedded system design methods based on parameterized systems on a chip (SOCs). It proposes a strategy for exploration of the configuration space of a parameterized SOC architecture to determine an accurate approximation of the power/performance Pareto-front. The strategy is based on genetic algorithms and is thoroughly evaluated in terms of ac... View full abstract»

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  • On effective slack management in postscheduling phase

    Publication Year: 2005, Page(s):645 - 653
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, we propose techniques for effective slack management in high-level synthesis. Our design methodology improves the usability of slack. This manifests itself in the form of relaxed latency constraints on resources. Relaxed latency constraints could be exploited to generate designs with better power, area, routability, and other measures. The slack-management engine has two key compone... View full abstract»

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  • On the numerical stability of Green's function for substrate coupling in integrated circuits

    Publication Year: 2005, Page(s):653 - 658
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    This paper presents an analysis of the numerical stability for the formulation of the Green's function method of Niknejad et al. (1998) for modeling and analysis of substrate coupling in integrated circuits. It is shown that the formulation has numerical overflow problems. A new stable formulation is presented. View full abstract»

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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 659
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  • IEEE Member Digital Library

    Publication Year: 2005, Page(s): 660
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu